V363EPC Просмотр технического описания (PDF) - QuickLogic Corporation

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V363EPC

Local Bus to PCI Bridge for Embedded Processors

QuickLogic Corporation 

Pin Descriptions and Pinouts

Table 3: Signal Descriptions: Non-Processor Mode Dependent

Signal

Type

IDSEL

PCI I

REQ

GNT

PCLK

PRST

PCI O

PCI I

PCI I

PCI I/O

PERR

PCI I/O

SERR

PCI I/OD

INT[A:D] PCI I/OD

SCL/LPERR

O4

SDA

I/O4

RDIR

I

VCC

—

GND

—

Reset

State

Description

Initialization Device Select is used as a chip select during

configuration read and write transactions. It must be driven high in

order to access the chip’s internal configuration space.

Z

Request indicates to the arbiter that this agent requests use of the

bus.

Grant indicates to the agent that access to the bus has been

granted.

PCI Clock provides timing for all transactions on the PCI bus.

PCI Reset acts as an input when RDIR is high, an output when

Z/L RDIR is low. As an input it is asserted low to bring all internal EPC

operation to a reset state.

Z

Parity Error is used to report data parity errors during all PCI

transactions except a Special Cycle.

System Error is used to report address parity errors, data parity

Z errors on the Special Cycle command, or any other system error

where the result will be catastrophic.

Z

Interrupt is used to receive or generate level-sensitive interrupt

requests.

Serial EEPROM Interface Signals

X EEPROM Clock, Local Parity Error.

X EEPROM Data.

Configuration Signal

Reset Direction: tie low to drive PRST out and LRST in; tie high to

drive LRST out and PRST in.

Power and Ground Signals

Power leads for external connection to a 3.3 V VCC board plane.

Ground leads for external connection to a GND board plane.

© 2000 V3 Semiconductor Corp.

V363EPC A0 Data Sheet Rev 1.01 DS-EC301-0101

5

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