V363EPC Просмотр технического описания (PDF) - QuickLogic Corporation
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V363EPC Datasheet PDF : 23 Pages
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Pin Descriptions and Pinouts
3.0 Pin Descriptions and Pinouts
Table 2 lists the pin types found on the V363EPC. Together, Table 3 and Table 4 describe the function of each pin on
the V363EPC. Table 5 lists the RESET state for test mode pins. Section 3.2 lists processor-mode-specific pin
assignments and shows the pinouts for the 160-pin EIAJ PQFP package. Figure 6 shows the mechanical dimensions
of the package.
Table 2: Pin Types
Pin Type
PCI I
PCI O
PCI I/O
PCI I/OD
I/O4
I
O4
Description
PCI input only pin.
PCI output only pin.
PCI tri-state I/O pin.
PCI input with open drain output.
TTL I/O pin with 4 mA output drive.
TTL input only pin.
TTL output pin with 4 mA output drive.
Table 3: Signal Descriptions: Non-Processor Mode Dependent
Signal
AD[31:0]
C/BE[3:0]
PAR
FRAME
IRDY
TRDY
STOP
DEVSEL
Type
PCI I/O
PCI I/O
PCI I/O
PCI I/O
PCI I/O
PCI I/O
PCI I/O
PCI I/O
Reset
State
Z
Z
Z
Z
Z
Z
Z
Z
Description
PCI Bus Interface Signals
Address and Data multiplexed on the same pins.
Bus Command and Byte Enables multiplexed on the same pins.
Parity represents even parity across AD[31:0] and C/BE[3:0].
Cycle Frame indicates the beginning and burst length of an access.
Initiator Ready indicates the initiating agent’s (bus master’s) ability
to complete the current data phase of the transaction.
Target Ready indicates the target agent’s (selected device’s) ability
to complete the current data phase of the transaction.
Stop indicates that the current target is requesting the master to stop
the current transaction (retry or disconnect).
Device Select, when actively driven by a target, indicates the driving
device has decoded its address as the target of the current access.
As an input to the initiator, DEVSEL indicates whether any device on
the bus has been selected.
4
V363EPC A0 Data Sheet Rev 1.01 DS-EC301-0101
© 2000 V3 Semiconductor Corp.
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