V363EPC Просмотр технического описания (PDF) - QuickLogic Corporation
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V363EPC Datasheet PDF : 23 Pages
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About the V363EPC
The V363EPC offers the highest performance, most flexible, and most economical solution for interfacing either
32-bit or 16-bit local bus applications to the PCI bus. It is also an ideal candidate for a variety of high-performance
applications based on Motorola, IBM, DEC, Hitachi, and other popular embedded processors where only a minimal
amount of glue logic is needed.
V363EPC is the 3.3 V enhanced version of the V350EPC and V360EPC Rev A1 devices and supports powerful
features like Hot Swap and DMA chaining. The PCI bus operates at up to 50 MHz, independent of local bus clock
frequency. The overall throughput of the system is dramatically improved by using our unique Dynamic Bandwidth
Allocation™ architecture.
Access to the PCI bus can be performed through two programmable address apertures. Two more apertures are
provided for PCI-to-local bus accesses. There are 64 bytes of read FIFOs in each direction, 32 bytes dedicated for
each aperture.
Two high-performance DMA channels with chaining and demand mode capabilities provide a powerful data transfer
engine for bulk data transfers. Mailbox registers and flexible PCI interrupt controllers also provide a simple
mechanism to emulate PCI device control ports. The part is available in a 160-pin, low-cost PQFP package.
This document contains the product codes, pinouts, package mechanical information, DC characteristics, and AC
characteristics for the V363EPC. Detailed functional information is contained in the User’s Manual.
Note: V3 Semiconductor retains the rights to change documentation, specifications, or
device functionality at any time without notice. Please verify that you have the latest copy
of all documents before finalizing a design.
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V363EPC A0 Data Sheet Rev 1.01 DS-EC301-0101
© 2000 V3 Semiconductor Corp.
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