V363EPC Просмотр технического описания (PDF) - QuickLogic Corporation
Номер в каталоге
Компоненты Описание
производитель
V363EPC Datasheet PDF : 23 Pages
| |||
V363EPC A0 Data Sheet
V363EPC A0 Local Bus to PCI Bridge
for Embedded Processors
1.0 About the V363EPC
w Direct interface to these processors:
• AMD® AM29030/40™
• IBM® PowerPC 401™ Gx
• Intel® i960® Cx/Hx/Jx/Sx
w Fully compliant with PCI Local Bus
Specification, Revision 2.1
w Configurable for system master, PCI bus
master, or PCI target operation
w Type 0 and Type 1 PCI configuration cycles
w Up to 1 kB burst access on the PCI or
the local bus
w 640 bytes of programmable FIFO storage with
Dynamic Bandwidth Allocation™ architecture
w 64-byte read FIFO in each direction
w Enhanced support for 8-bit/16-bit local bus
devices with programmable region sizes
w Dual bi-directional address space remapping
w 10-bit bus watch timer
w On-the-fly byte order (endian) conversion
w I2O-Ready™ ATU and messaging unit,
including hardware controlled circular queues
w Two-channel DMA, multiprocessor DMA
chaining, and demand mode DMA
w Hot Swap Capable™ according to the PICMG®
Hot Swap Specification, version 2.1
w Sixteen 8-bit bi-directional mailbox registers
with doorbell interrupts
w Support for real-mode MS-DOS® holes
w Flexible PCI and local interrupt management
w Optional power-on serial EEPROM
initialization
w Up to 50 MHz on both PCI and local bus clocks
w 3.3 V operation; 5 V tolerant input
w Industrial temperature range (−40°C to +85°C)
w Low-cost 160-pin EIAJ PQFP package
(Electronic Industries Association of Japan
Plastic Quad Flat Pack)
© 2000 V3 Semiconductor Corp.
V363EPC A0 Data Sheet Rev 1.01 DS-EC301-0101
1
Share Link: 