ML4669IQ Просмотр технического описания (PDF) - Micro Linear Corporation

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ML4669IQ

10BASE-FL to 10BASE-T Converter

Micro Linear Corporation 

SYSTEM DESCRIPTION (Continued)

TPOUTP and TPOUTN, can drive a 100W, 150W load, or

a variety of impedances that are characteristic of the

twisted pair wire. RTSETTP selects the current into the

TPOUTP, TPOUTN pins. This current along with the

characteristic impedance of the cable determines the

output voltage.

Once the characteristic impedance of the twisted pair is

determined, one must select the appropriate RTSETTP

resistor as well as match the terminating impedances of

the transmit and receive filter. The RTSETTP resistor can

be selected as follows:

  W RTSETTP = RL ™ 220

  100

(2)

Where RL is the characteristic impedance of the twisted

pair cable.

The transmitter incorporates a pre-equalization circuit for

driving the twisted pair line. Pre-equalization

compensates for the amplitude and phase distortion

introduced by the twisted pair cable. The twisted pair line

will attenuate the 10MHz signal more than the 5MHz

signal. Therefore pre-equalization insures that both the 5

and 10MHz components will be roughly the same

amplitude at the far end receiver.

The pre-equalization circuit reduces the current output

when a 5MHz bit is being transmitted. After 50ns of a

5MHz bit, the current level is reduced to approximately

2/3 of its peak for the remaining 50ns. Figure 9 illustrates

the pre-equalization.

An on-chip one-shot determines the pulse width of the

pre-equalized transmit signal. This requires an external

capacitor connected to pins TxCAP0 and TxCAP1. The

proper value for this one-shot is 680pF. Pre-equalization

can be disabled by shorting TxCAP0 and TxCAP1 together.

The transmitter enters the idle state when it detects start

of idle on OPINP and OPINN input pins. The transmitter

maintains a minimum differential output voltage of at

least 450mV for 250ns after the last low to high transition.

The driver differential output voltage will then be within

50mV of 0V within 45 bit times.

OP SQUELCH

The input to the optical receiver comes from a fiber optic

pre-amp. At the start of packet reception no more than

2.7 bits are received from the fiber cable and not

transmitted onto the TP outputs. The receive squelch will

reject frequencies lower than 2.51MHz.

ML4664/ML4669

While in the unsquelch state, the receive squelch circuit

looks for the start of idle signal at the end of the packet.

Start of idle occurs when the input signal remains idle for

more than 160ns. When start of idle is detected, the

receive squelch circuit returns to the squelch state and the

start of idle signal is output on the twisted pair outputs

TPOUTP, TPOUTN.

INPUT AMPLIFIER

The OPINP, OPINN input signal is fed into a limiting

amplifier with a gain of about 100 and input resistance of

1.3kW. Maximum sensitivity is achieved through the use

of a DC restoration feedback loop and AC coupling the

input. When AC coupled, the input DC bias voltage is set

by an on-chip network at about 1.7V. These coupling

capacitors, in conjunction with the input impedance of

the amplifier, establish a high pass filter with 3dB corner

frequency, fL, at:

fL =

1

2p ™ 1300 C

(3)

Since the amplifier has a differential input, two capacitors

of equal value are required. If the signal driving the input

is single ended, one of the coupling capacitors can be

tied to AVCC.

The internal amplifier has a lowpass filter built-in to band

limit the input signal which in turn will improve the

signal to noise ratio.

Although the input is AC coupled, the offset voltage

within the amplifier will be present at the amplifier’s

output. In order to reduce this error a DC feedback loop

is incorporated. This negative feedback loop nulls the

offset voltage, forcing VOS to be zero. Although the

capacitor on VDC is non-critical, the pole it creates can

effect the stability of the feedback loop. To avoid stability

problems, the value of this capacitor should be at least 10

times larger than the input coupling capacitors.

The comparator is a high-speed differential zero crossing

detector that slices and accurately digitizes the receive

signal. The output of the comparator is fed into the

receive squelch circuit.

11

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