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GBE-PCS-PM-U1 Просмотр технического описания (PDF) - Lattice Semiconductor

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GBE-PCS-PM-U1
Lattice
Lattice Semiconductor Lattice
GBE-PCS-PM-U1 Datasheet PDF : 17 Pages
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Lattice Semiconductor
Gigabit Ethernet PCS IP Core
for LatticeECP2M
Table 1. GbE PCS IP Core Input and Output Signals (Continued)
Signal Name
correct_disp
xmit_autoneg
rx_data[7:0]
rx_kcntl
I/O
Description
Corrects Disparity – Asserted during inter-packet gaps to ensure that negative dispar-
Out ity IDLE ordered-sets are transmitted by the LatticeECP2M embedded SERDES /PCS.
1=correct disparity, 0=normal
Auto-negotiation Transmitting – This signal asserts when the IP core’s auto negotia-
tion state machine is active. The signal is used by the LatticeECP2M embedded SER-
Out DES/PCS to occasionally insert idle ordered sets into its receive path (eight ordered
sets every 2048 clocks). This facilitates proper operation of the embedded clock toler-
ance compensation circuit. 1=autoneg is active, 0=autoneg is not active
In 8b Receive Data – 8-bit code group data presented to the receive state machine.
In
8b Receive K Control – Denotes whether current code group is data or control.
1=control 0=data
Receive Error Control Mode – The embedded SERDES block of the LatticeECP2M
FPGAs has two modes of interpreting errors, decoded and normal. In decoded mode,
the three signals (rx_even, rx_cv_err, rx_disp_err) are used to decode 1-of-8 error
conditions. In decoded mode, the IP core responds to the following errors:
rx_err_decode_mode
In 100 = Coding Violation Error
111 = Disparity Error
rx_even
rx_cv_err
rx_disp_err
signal_detect
Management Signals
mr_adv_ability[15:0]
mr_an_enable
mr_main_reset
mr_restart_an
mr_an_complete
All other error codes are ignored by the IP core. In normal mode, the three error signals
(rx_even, rx_cv_err, rx_disp_err) behave normally. The rx_err_decode_mode
signal should be set high for decode mode, and low for normal mode.
In
Rx Even – This signal is only used when error decoding mode is active. Otherwise, the
signal should be tied low.
Rx Coding Violation Error – In normal mode, an active high signal denoting a coding
In violation error in the receive data path. In decode mode, used to decode 1 of 8 error
conditions.
In
Rx Disparity Error – In normal mode, an active high signal denoting a disparity error in
the receive data path. In decode mode, used to decode 1 of 8 error conditions.
In
Signal Detect – Denotes status of GbE PCS RX physical link. 1=signal is good; 0=loss
of receive signal
In
Advertised Ability – Configuration status transmitted by PCS during auto negotiation
process.
In
Auto Negotiation Enable – Active high signal that enables auto negotiation state
machine to function.
In Main Reset – Active high signal that forces all PCS state machines to reset.
In
Auto Negotiation Restart – Active high signal that forces auto negotiation process to
restart.
Out
Auto Negotiation Complete – Active high signal that indicates that the auto negotia-
tion process is completed.
Link Partner Advertised Ability – Configuration status received from partner PCS
mr_lp_adv_ability[15:0] Out entity during the auto negotiating process. The bit definitions are the same as
described above for the mr_adv_ability port.
mr_page_rx
Out
Auto Negotiation Page Received – Active high signal that asserts while the auto
negotiation state machine is in the Complete_Acknowledge state.
Miscellaneous Signals
rst_n
debug_link_timer_short
In Reset – Active low global reset
Debug Link Timer Mode – Active high signal that forces the auto negotiation link timer
In
to run much faster than normal. This mode is provided for debug purposes (e.g.,allow-
ing simulations to run through the auto negotiation process much faster that the nor-
mal).
5

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