AD9216BCPZ-65 Просмотр технического описания (PDF) - Analog Devices
Номер в каталоге
Компоненты Описание
производитель
AD9216BCPZ-65 Datasheet PDF : 40 Pages
| |||
AD9216
SWITCHING SPECIFICATIONS
AVDD = 3.0 V, DRVDD = 2.5 V, maximum sample rate, CLK_A = CLK_B; AIN = −0.5 dBFS differential input, 1.0 V internal reference,
TMIN to TMAX, DCS enabled, unless otherwise noted.
Table 4.
Parameter
SWITCHING PERFORMANCE
Maximum Conversion Rate
Minimum Conversion Rate
CLK Period
CLK Pulse Width High
CLK Pulse Width Low
OUTPUT PARAMETERS1
Output Propagation Delay2 (tPD)
Valid Time3 (tV)
Output Rise Time (10% to 90%)
Output Fall Time (10% to 90%)
Output Enable Time4
Output Disable Time4
Pipeline Delay (Latency)
APERTURE
Aperture Delay (tA)
Aperture Uncertainty (tJ)
Wake-Up Time5
OUT-OF-RANGE RECOVERY TIME
AD9216BCPZ-65 AD9216BCPZ-80 AD9216BCPZ-105
Temp Test Level Min Typ Max Min Typ Max Min Typ Max Unit
Full VI
Full IV
Full VI
Full VI
Full VI
65
80
105
10
10
15.4
12.5
9.5
4.6
4.4
3.8
4.6
4.4
3.8
MSPS
10 MSPS
nS
nS
nS
25°C I
25°C I
25°C V
25°C V
Full IV
Full IV
Full IV
4.5 6.4
4.5 6.4
4.5 6.4 nS
2.0
2.0
2.0
1.0
1.0
1.0
nS
1.0
1.0
1.0
nS
1
1
1
Cycle
1
1
1
Cycle
6
6
6
Cycle
25°C V
25°C V
25°C V
25°C V
1.5
1.5
1.5
nS
0.5
0.5
0.5
pS rms
7
7
7
ms
1
1
1
Cycle
1 CLOAD equals 5 pF maximum for all output switching parameters.
2 Output delay is measured from clock 50% transition to data 50% transition.
3 Valid time is approximately equal to the minimum output propagation delay.
4 Output enable time is OEB_A, OEB_B falling to respective channel outputs coming out of high impedance. Output disable time is OEB_A, OEB_B rising to respective
channel outputs going into high impedance.
5 Wake-up time is dependent on value of decoupling capacitors; typical values shown for 0.1 µF and 10 µF capacitors on REFT and REFB.
Rev. A | Page 6 of 40
Share Link: 