PHD98N03LT Просмотр технического описания (PDF) - NXP Semiconductors.
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PHD98N03LT Datasheet PDF : 12 Pages
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NXP Semiconductors
PHD98N03LT
N-channel TrenchMOS logic level FET
2.5
VGS(th)
(V)
2
1.5
1
03aa33
max
typ
min
10-1
ID
(A)
10-2
10-3
10-4
03aa36
min
typ
max
0.5
10-5
0
-60
0
60
120
180
Tj (°C)
10-6
0
1
2
3
VGS (V)
ID = 1 mA; VDS = VGS
Fig 9. Gate-source threshold voltage as a function of
junction temperature
Tj = 25 °C; VDS = 5 V
Fig 10. Sub-threshold drain current as a function of
gate-source voltage
10
VGS
(V)
8
ID = 50 A
Tj = 25 °C
VDS = 15 V
6
003aab663
4
2
0
0
40
80 QG (nC) 120
ID = 50 A; VDS = 15 V
Fig 11. Gate-source voltage as a function of gate
charge; typical values
VDS
ID
VGS(pl)
VGS(th)
VGS
QGS1 QGS2
QGS
QGD
QG(tot)
003aaa508
Fig 12. Gate charge waveform definitions
PHD98N03LT_5
Product data sheet
Rev. 05 — 1 December 2006
© NXP B.V. 2006. All rights reserved.
7 of 12
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