PHD98N03LT Просмотр технического описания (PDF) - NXP Semiconductors.
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PHD98N03LT Datasheet PDF : 12 Pages
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NXP Semiconductors
120
Pder
(%)
80
03aa16
PHD98N03LT
N-channel TrenchMOS logic level FET
120
Ider
(%)
80
003aab655
40
40
0
0
50
100
150
200
Tmb (°C)
Pder = P----t--o--P-t-(--t2-o--5-t-°---C---) × 100 %
Fig 1. Normalized total power dissipation as a
function of mounting base temperature
103
ID
(A)
102
Limit RDSon = VDS / ID
DC
10
0
0
50
100
150
200
Tmb (°C)
Ider = -I--D----(-I-2-D-5---°--C---) × 100 %
Fig 2. Normalized continuous drain current as a
function of mounting base temperature
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tp = 10 ms
100 ms
1 ms
10 ms
100 ms
1
1
10
102
VDS (V)
Tmb = 25 °C; IDM is single pulse
Fig 3. Safe operating area; continuous and peak drain currents as a function of drain-source voltage
PHD98N03LT_5
Product data sheet
Rev. 05 — 1 December 2006
© NXP B.V. 2006. All rights reserved.
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