PHD98N03LT Просмотр технического описания (PDF) - NXP Semiconductors.
Номер в каталоге
Компоненты Описание
производитель
PHD98N03LT Datasheet PDF : 12 Pages
| |||
NXP Semiconductors
PHD98N03LT
N-channel TrenchMOS logic level FET
3. Ordering information
Table 2. Ordering information
Type number
Package
Name
PHD98N03LT
DPAK
Description
plastic single-ended surface-mounted package; 3 leads
(one lead cropped)
4. Limiting values
Table 3. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter
Conditions
Min
VDS
drain-source voltage
25 °C ≤ Tj ≤ 175 °C
-
VDGR drain-gate voltage (DC)
25 °C ≤ Tj ≤ 175 °C; RGS = 20 kΩ
-
VGS
gate-source voltage
-
ID
drain current
Tmb = 25 °C; VGS = 5 V; see Figure 2 and 3
-
Tmb = 100 °C; VGS = 5 V; see Figure 2
-
IDM
peak drain current
Tmb = 25 °C; pulsed; tp ≤ 10 µs; see Figure 3
-
Ptot
total power dissipation
Tmb = 25 °C; see Figure 1
-
Tstg
storage temperature
−55
Tj
junction temperature
−55
Source-drain diode
IS
source current
Tmb = 25 °C
-
ISM
peak source current
Tmb = 25 °C; pulsed; tp ≤ 10 µs
-
Avalanche ruggedness
EDS(AL)S non-repetitive drain-source
unclamped inductive load; ID = 43 A;
-
avalanche energy
tp = 0.27 ms; VDS = 15 V; RGS = 50 Ω; VGS = 5 V;
starting at Tj = 25 °C
Version
SOT428
Max Unit
25
V
25
V
±20
V
75
A
66
A
240
A
111
W
+175 °C
+175 °C
75
A
240
A
183
mJ
PHD98N03LT_5
Product data sheet
Rev. 05 — 1 December 2006
© NXP B.V. 2006. All rights reserved.
2 of 12
Share Link: 