QG82945GMESLA9H Просмотр технического описания (PDF) - Intel
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QG82945GMESLA9H Datasheet PDF : 319 Pages
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4.2.11 C0DRC1—Channel A DRAM Controller Mode 1 ............................... 100
4.2.12 C1DRB0—Channel B DRAM Rank Boundary Address 0 .................. 100
4.2.13 C1DRB1—Channel B DRAM Rank Boundary Address 1 .................. 100
4.2.14 C1DRB2—Channel B DRAM Rank Boundary Address 2 .................. 100
4.2.15 C1DRB3—Channel B DRAM Rank Boundary Address 3 .................. 101
4.2.16 C1DRA0—Channel B DRAM Rank 0,1 Attribute ............................... 101
4.2.17 C1DRA2—Channel B DRAM Rank 2,3 Attribute ............................... 101
4.2.18 C1DCLKDIS—Channel B DRAM Clock Disable ................................ 101
4.2.19 C1BNKARC—Channel B Bank Architecture ...................................... 101
4.2.20 C1DRT1—Channel B DRAM Timing Register 1 ................................ 102
4.2.21 C1DRC0—Channel B DRAM Controller Mode 0 ............................... 102
4.2.22 C1DRC1—Channel B DRAM Controller Mode 1 ............................... 102
4.2.23 PMCFG—Power Management Configuration .................................... 102
4.2.24 PMSTS—Power Management Status ................................................ 103
4.3 EPBAR Registers—Egress Port Register Summary ......................................... 104
4.3.1 EPESD—EP Element Self Description............................................... 105
4.3.2 EPLE1D—EP Link Entry 1 Description .............................................. 106
4.3.3 EPLE1A—EP Link Entry 1 Address.................................................... 107
4.3.4 EPLE2D—EP Link Entry 2 Description .............................................. 107
4.3.5 EPLE2A—EP Link Entry 2 Address.................................................... 108
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Host-PCI Express* Bridge Registers (D1:F0) (Intel® 82945G/82945GC/82945P/82945PL
Only)................................................................................................................................ 109
5.1 Configuration Register Details (D1:F0) .............................................................. 112
5.1.1 VID1—Vendor Identification (D1:F0) .................................................. 112
5.1.2 DID1—Device Identification (D1:F0) .................................................. 112
5.1.3 PCICMD1—PCI Command (D1:F0) ................................................... 113
5.1.4 PCISTS1—PCI Status (D1:F0)........................................................... 115
5.1.5 RID1—Revision Identification (D1:F0)................................................ 116
5.1.6 CC1—Class Code (D1:F0) ................................................................. 116
5.1.7 CL1—Cache Line Size (D1:F0) .......................................................... 117
5.1.8 HDR1—Header Type (D1:F0) ............................................................ 117
5.1.9 PBUSN1—Primary Bus Number (D1:F0) ........................................... 117
5.1.10 SBUSN1—Secondary Bus Number (D1:F0) ...................................... 118
5.1.11 SUBUSN1—Subordinate Bus Number (D1:F0) ................................. 118
5.1.12 IOBASE1—I/O Base Address (D1:F0) ............................................... 119
5.1.13 IOLIMIT1—I/O Limit Address (D1:F0) ................................................ 119
5.1.14 SSTS1—Secondary Status (D1:F0) ................................................... 120
5.1.15 MBASE1—Memory Base Address (D1:F0)........................................ 121
5.1.16 MLIMIT1—Memory Limit Address (D1:F0) ......................................... 122
5.1.17 PMBASE1—Prefetchable Memory Base Address (D1:F0) ................ 123
5.1.18 PMLIMIT1—Prefetchable Memory Limit Address (D1:F0) ................. 124
5.1.19 CAPPTR1—Capabilities Pointer (D1:F0) ........................................... 124
5.1.20 INTRLINE1—Interrupt Line (D1:F0) ................................................... 125
5.1.21 INTRPIN1—Interrupt Pin (D1:F0) ....................................................... 125
5.1.22 BCTRL1—Bridge Control (D1:F0) ...................................................... 126
5.1.23 PM_CAPID1—Power Management Capabilities (D1:F0) .................. 128
5.1.24 PM_CS1—Power Management Control/Status (D1:F0) .................... 129
5.1.25 SS_CAPID—Subsystem ID and Vendor ID Capabilities (D1:F0) ...... 130
5.1.26 SS—Subsystem ID and Subsystem Vendor ID (D1:F0) .................... 130
5.1.27 MSI_CAPID—Message Signaled Interrupts Capability ID (D1:F0) .... 131
5.1.28 MC—Message Control (D1:F0) .......................................................... 132
5.1.29 MA—Message Address (D1:F0)......................................................... 133
Intel® 82945G/82945G/82945GC GMCH and 82945P/82945PL MCH Datasheet
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