LH28F016SC-L Просмотр технического описания (PDF) - Sharp Electronics
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LH28F016SC-L Datasheet PDF : 44 Pages
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12 V VPP) independent of other blocks. Each block
can be independently erased 100 000 times (3.2
million block erases per device). Block erase
suspend mode allows system software to suspend
block erase to read data from, or write data to any
other block.
Writing memory data is performed in byte
increments typically within 6 µs (5 V VCC, 12 V
VPP). Byte write suspend mode enables the system
to read data from, or write data to any other flash
memory array location.
Individual block locking uses a combination of bits,
thirty-two block lock-bits and a master lock-bit, to
lock and unlock blocks. Block lock-bits gate block
erase and byte write operations, while the master
lock-bit gates block lock-bit modification. Lock-bit
configuration operations (Set Block Lock-Bit, Set
Master Lock-Bit, and Clear Block Lock-Bits
commands) set and cleared lock-bits.
The status register indicates when the WSM’s block
erase, byte write, or lock-bit configuration operation
is finished.
The RY/BY# output gives an additional indicator of
WSM activity by providing both a hardware signal
of status (versus software polling) and status
masking (interrupt masking for background block
erase, for example). Status polling using RY/BY#
minimizes both CPU overhead and system power
consumption. When low, RY/BY# indicates that the
WSM is performing a block erase, byte write, or
lock-bit configuration. RY/BY#-high indicates that
the WSM is ready for a new command, block erase
is suspended (and byte write is inactive), byte write
is suspended, or the device is in deep power-down
mode.
LH28F016SC-L/SCH-L
The access time is 95 ns (tAVQV) at the VCC supply
voltage range of 4.75 to 5.25 V over the
temperature range, 0 to +70°C (LH28F016SC-L)/
–40 to +85°C (LH28F016SCH-L). At 4.5 to 5.5 V
VCC, the access time is 100 ns or 120 ns. At lower
VCC voltage, the access time is 120 ns or 150 ns
(3.0 to 3.6 V) and 150 ns or 170 ns (2.7 to 3.6 V).
The Automatic Power Saving (APS) feature
substantially reduces active current when the
device is in static mode (addresses not switching).
In APS mode, the typical ICCR current is 1 mA at
5 V VCC and 3 mA at 2.7 V and 3.3 V VCC.
When CE# and RP# pins are at VCC, the ICC
CMOS standby mode is enabled. When the RP#
pin is at GND, deep power-down mode is enabled
which minimizes power consumption and provides
write protection during reset. A reset time (tPHQV) is
required from RP# switching high until outputs are
valid. Likewise, the device has a wake time (tPHEL)
from RP#-high until writes to the CUI are
recognized. With RP# at GND, the WSM is reset
and the status register is cleared.
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