LH28F016SC-L Просмотр технического описания (PDF) - Sharp Electronics
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LH28F016SC-L Datasheet PDF : 44 Pages
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LH28F016SC-L/SCH-L
3.6 Write
Writing commands to the CUI enable reading of
device data and identifier codes. They also control
inspection and clearing of the status register. When
VPP = VPPH1/2/3, the CUI additionally controls
block erasure, byte write, and lock-bit configuration.
The Block Erase command requires appropriate
command data and an address within the block to
be erased. The Byte Write command requires the
command and address of the location to be written.
Set Master and Block Lock-Bit commands require
the command and address within the device
(Master Lock) or block within the device (Block
Lock) to be locked. The Clear Block Lock-Bits
command requires the command and address
within the device.
The CUI does not occupy an addressable memory
location. It is written when WE# and CE# are
active. The address and data needed to execute a
command are latched on the rising edge of WE# or
CE# (whichever goes high first). Standard
microprocessor write timings are used. Fig. 14 and
Fig. 15 illustrate WE# and CE#-controlled write
operations.
4 COMMAND DEFINITIONS
When the VPP voltage ≤ VPPLK, read operations
from the status register, identifier codes, or blocks
are enabled. Placing VPPH1/2/3 on VPP enables
successful block erase, byte write and lock-bit
configuration operations.
Device operations are selected by writing specific
commands into the CUI. Table 3 defines these
commands.
Table 2 Bus Operations
MODE
Read
Output Disable
Standby
Deep Power-Down
Read Identifier Codes
Write
NOTE RP#
1, 2, 3, 8 VIH or VHH
3 VIH or VHH
3 VIH or VHH
4
VIL
8 VIH or VHH
3, 6, 7, 8 VIH or VHH
CE#
VIL
VIL
VIH
X
VIL
VIL
OE#
VIL
VIH
X
X
VIL
VIH
WE# ADDRESS VPP DQ0-7 RY/BY#
VIH
X
X
DOUT
X
VIH
X
X High Z X
X
X
X High Z X
X
X
X
High Z VOH
VIH See Fig. 2 X (NOTE 5) VOH
VIL
X
X
DIN
X
NOTES :
1. Refer to Section 6.2.3 "DC CHARACTERISTICS".
When VPP ≤ VPPLK, memory contents can be read, but
not altered.
2. X can be VIL or VIH for control pins and addresses, and
VPPLK or VPPH1/2/3 for VPP. See Section 6.2.3 "DC
CHARACTERISTICS" for VPPLK and VPPH1/2/3 voltages.
3. RY/BY# is VOL when the WSM is executing internal
block erase, byte write, or lock-bit configuration
algorithms. It is VOH during when the WSM is not busy,
in block erase suspend mode (with byte write inactive),
byte write suspend mode, or deep power-down mode.
4. RP# at GND±0.2 V ensures the lowest deep power-
down current.
5. See Section 4.2 for read identifier code data.
6. Command writes involving block erase, byte write, or
lock-bit configuration are reliably executed when VPP =
VPPH1/2/3 and VCC = VCC2/3/4. Block erase, byte write, or
lock-bit configuration with VCC < 3.0 V or VIH < RP# <
VHH produce spurious results and should not be
attempted.
7. Refer to Table 3 for valid DIN during a write operation.
8. Don't use the timing both OE# and WE# are VIL.
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