MC141516FJ Просмотр технического описания (PDF) - Motorola => Freescale
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MC141516FJ Datasheet PDF : 16 Pages
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PIN DESCRIPTIONS
Pin Locations
85
84
83
(a) 51, 52, 53, 56, 57, 58, 59, 62, 63
(b) 68, 69, 72, 73, 74, 75, 78, 79, 80
(c) 1, 2, 3, 6, 7, 8, 9, 12, 13
(d) 18, 19, 22, 23, 24, 25, 28, 29, 30
86
89
31
32, 33, 34, 35, 44, 45, 46,
47, 48, 49, 50, 81, 82, 99, 100
36, 37
93, 94, 95, 96
(a) (b) (c) (d)
98
97
92
88
87
64
15, 41, 65, 91
4, 11, 20, 27, 54, 61, 70, 77
5, 10, 17, 21, 26, 40,
55, 60, 67, 71, 76, 90
14, 16, 38, 39, 42, 43, 66
Symbol
ADSC
ADSP
ADV
DQx
Type
Input
Input
Input
I/O
Description
Synchronous Address Status Controller: Active low, interrupts any
ongoing burst and latches a new external address. Used to initiate a
READ, WRITE, or chip deselect.
Synchronous Address Status Processor: Active low, interrupts any
ongoing burst and latches a new external address. Used to initiate a
new READ, WRITE, or chip deselect (exception — chip deselect
does not occur when ADSP is asserted and SE1 is high).
Synchronous Address Advance: Increments address count in
accordance with counter type selected (linear/interleaved).
Synchronous Data I/O: “x” refers to the byte being read or written
(byte a, b, c, d).
G
K
LBO
SA
SA1, SA0
SBx
SE1
SE2
SE3
SGW
SW
ZZ
VDD
VDDQ
VSS
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Supply
Supply
Supply
Asynchronous Output Enable Input.
Clock: This signal registers the address, data in, and all control
signals except G, LBO, and ZZ.
Linear Burst Order Input: This pin may be left floating; it will default
as interleaved.
Low — linear burst counter (68K/PowerPC).
High — interleaved burst counter (486/i960/Pentium).
Synchronous Address Inputs: These inputs are registered and must
meet setup and hold times.
Synchronous Address Inputs: These pins must be wired to the two
LSBs of the address bus for proper burst operation. These inputs
are registered and must meet setup and hold times.
Synchronous Byte Write Inputs: “x” refers to the byte being written
(byte a, b, c, d). SGW overrides SBx.
Synchronous Chip Enable: Active low to enable chip.
Negated high — blocks ADSP or deselects chip when ADSC is
asserted.
Synchronous Chip Enable: Active high for depth expansion.
Synchronous Chip Enable: Active low for depth expansion.
Synchronous Global Write: This signal writes all bytes regardless of
the status of the SBx and SW signals. If only byte write signals SBx
are being used, tie this pin high.
Synchronous Write: This signal writes only those bytes that have
been selected using the byte write SBx pins. If only byte write
signals SBx are being used, tie this pin low.
Sleep Mode: This active high asynchronous signal places the RAM
into the lowest power mode. The ZZ pin disables the RAMs internal
clock when placed in this mode. When ZZ is negated, the RAM
remains in low power mode until it is commanded to READ or
WRITE. Data integrity is maintained upon returning to normal
operation.
Core Power Supply.
I/O Power Supply.
Ground.
NC
—
No Connection: There is no connection to the chip.
MCM63P733A
4
MOTOROLA FAST SRAM
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