MU9C8248QEC Просмотр технического описания (PDF) - Music Semiconductors
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MU9C8248QEC Datasheet PDF : 28 Pages
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MU9C8248
FUNCTIONAL DESCRIPTION (CONT’D)
register. The second 16-bit word is written to or read from the
/W, /CM, /EC, /SP, S, L2-L0 bits of that same location.
The Control register contains an Address pointer that selects
the accessed location in the IS (location 00H-3FH) and DS
(location 40H-7FH). The Address pointer can be read out or
overwritten. It is incremented when the Host processor has
completed the two write or read cycles to/from one location of
the IB.
The TBB starts Routine 0 and/or 1 when the enable bit of that
routine is set HIGH. Routines 0, used for DA and SA
comparison is started directly after the SD has been received
or is started with a delay if this is programmed in the delay bits
of the FIFO Control/Delay register, while Routine 1, used for
the learning of network addresses, is started after the Error
indicator of the FS field has been received.
Arbiter
Execution of Routines
Routines in the instruction buffer can be started either by the
Host processor (Routines 2-5 only) or the Transparent Bridging
Block (Routines 0-1 only). If a routine is started by the Host
processor, it is started immediatly if the arbiter allows it.
Otherwise the start is delayed as long as necessary.
The Arbiter block has two tasks: 1) Arbitration between the
execution of different routines stored in the Instruction Buffer,
2) Arbitration between the execution of routines in the
Instruction buffer and Host Processor access to the LANCAM.
64 Locations
D15 - D0
Rev. 2.5 Web
LANCAM
Interface
Instruction
Pointer and
Control
64 Locations
/W, /CM, /EC, SP, S, L2 - L0
IB
Register
FIFO
Register
D15 - D0
Start
Address
Address
Pointer
FIFO
Control
Arbiter
TB block
10
TB
Register
Start
Address
Register
Control
Register
/WF,
/FFI
DF7 - DF0,
DFC
Figure 1: The Instruction Buffer
8
FIFO
Control/
Delay
Register
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