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MU9C8248

FDDI SRT Interface

Music Semiconductors 

MU9C8248

FUNCTIONAL DESCRIPTION (CONT’D)

The Source Address (SA) of a frame can be used to update the

database of addresses stored in the LANCAM. Routine 0 not

only checks the DA but also the SA of a frame against all the

entries in the database. If the SA is not found (the address is

new) and if the frame received is error free, the address can be

learned by adding it to the LANCAM database (by starting

Routine 1) and at the same time writing it into the internal or

external FIFO. The learning Routine 1 can be activated for

specific frame types by setting the bits MLRN-FSLRN HIGH in

the Transparent Briding/MAC register. Even SA's of erroneous

frames can be learned when bit NOER of the Control register is

programmed HIGH. If the SA is found in the database,

XSAMAT is asserted.

Note that learning can only take place when the RII of the

frame is ZERO, or for every frame when the TBO bit is HIGH.

Thus, Routine 0 (performing a DA and SA comparison) is

always started after the SD is received and stopped when the

results of the DA and SA comparison are not needed. Routine

1 is started by the TBB block after the Error Indicator of the

Frame Status field is received and all programmed conditions

are met.

Source Routing Block

The Source Routing Block (SRB) only decides to copy or

discard a frame if it contains an RIF.

When a frame is received, the SRB checks whether the Frame

Control field indicates if a Token (Restricted or Non Restricted)

is being received and no further processing is necessary. If a

regular frame is being received and its RII bit is HIGH, the SRB

signals the MAC interface, based on the frame type and the

settings in the Frame Type Selection register, either to discard

the frame; to continue to check the RIF of the frame, or to

accept the frame immediately thereby having the MAC

interface asserting XDAMAT.

If the RII is LOW, the SRB is not allowed to process the frame

any further and waits for the next frame to arrive.

If the Routing Type (RT) bits are equal to 0XXB, a

Specifically-Routed Frame (SRF) is being received, and should

be forwarded on the conditions shown in Table 1. If the RT bits

are equal to 10XB, the frame is an All Routes Explorer (ARE)

frame, and should be handled as shown in Table 1. If the RT

bits are equal to 11XB, the frame is a Spanning Tree Explorer

(STE) frame, and should be dealt with as shown in Table 1.

Also described in Table 1 are the conditions on which the Error

counters (Register 1DH) are incremented.

Instruction Buffer

The Instruction buffer (IB) shown in Figure 1 consists of the

following: the 64-entry Instruction Storage (IS), the 64-entry

Data Storage (DS), the Instruction pointer (IP), the Address

pointer, the Start address registers, the FIFO, and FIFO control

registers.

The IS can store up to six down-loaded routines which contain

instructions for the LANCAM to execute. The IS location

accessed by the Host Processor port is controlled by an

auto-incrementing Address pointer, which is part of the Control

register. Each instruction is a 16-bit LANCAM op-code or data

word along with 3 bits that indicate the level of /W, /CM, /EC

during the instruction. An S-bit is used to indicate whether this

entry is a LANCAM instruction or a MU9C8248 instruction. The

ST-bit indicates whether this instruction is the last instruction in

a routine while bits L2-L0 indicate the length of the instruction.

The Instruction pointer (IP) points to the instruction currently

being fetched. At the start of a routine (only for Routine 2-5) the

IP is loaded with the appropriate Start address after which the

IP is used for instruction prefetches during execution. At the

start of Routine 0 and 1 the IP points at the second instruction

address because of the standard instruction prefetch of the

Start address used for a fast start of Routine 0 and 1. The IP

can also be loaded from addresses contained in an instruction

itself. For example, when a “Wait for a match” instruction is

executed and no match has occurred, the IP is loaded with the

address of the next instruction to execute.

If a copy/discard decision is made based on the information in

the RIF the FDDI chip set is signalled by SRMAT. The SRB

examines the information contained in the Routing Control

Field (RCF) which is part of the RIF. If the length (LTH) bits of

the RCF indicate a length equal to zero, or contain an odd

length, or if the length of the RIF is longer than the allowed

length stored in the RIF Length register, reception of the frame

is stopped, and the SRB indicates that the frame is to be

discarded (SRMAT is not asserted). The D-bit of the RCF is

used by the SRB to correctly interpret the Routing Descriptors

(RDs) of the RIF.

The SRB provides for sixteen Ring(in)–Bridge–Ring(out)

combinations (LIN-BN-LOUT) stored in the Source Ring

Number register and Bridge/Destination Ring Number registers.

LIN is the LAN ID of the ring connected to that specific port,

while the BN(s) and LOUT(s) depend on the topology of the

network and the bridge design. The SRB provides for checks

between the LAN ring numbers and bridge numbers contained

in every RD with every LIN-BN-LOUT stored, allowing the user

to develop an SR(T) bridge with an internal virtual ring, or a

bridge with a Full Mesh architecture.

The Start Address registers contain the start addresses of all

six routines. When a routine is started (Routine 2-5), this

address is copied into the IP and execution is started while for

Routine 0 and 1 the IP is loaded with the second instruction of

that routine.

Part of the ID may be used as a FIFO for data storage. Data

from the routines can be moved either to or from the Host

Processor interface through the FIFO or new network

addresses can be moved into the FIFO by the learning

process. The functionallity of the /FULL or /EMPTY flag is

programmed in the FIFO Control register to prevent FIFO

overflow or underflow situations.

Programming of Routines

The IS is loaded and read through the IB register in two 16-bit

cycles. The first 16-bit cycle moves the data on the D15–D0

lines of the Host Processor interface into the data field of the

location in the IB indicated by the Address pointer in the

Control register, or vice-versa in case of a read from the IB

Rev. 2.5 Web

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