MU9C8248QEC Просмотр технического описания (PDF) - Music Semiconductors

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MU9C8248QEC

FDDI SRT Interface

Music Semiconductors 

MU9C8248

PIN DESCRIPTIONS (CONT’D)

/FULL, /EMPTY (Full/Empty, Output, Open Drain)

If part of the Instruction buffer in the MU9C8248 is configured

as a FIFO, this active-LOW pin can be configured to signal

whether the FIFO is full (all entries contain valid data) or empty

(no entry contains data). The definition of this signal is

programmed in the FIFO Control/Delay register.

/INTEL (HPI Selection, Input, TTL)

The /INTEL pin identifies which type of microcontroller is

connected to the Host Processor interface. This pin is set LOW

for Intel-type addressing modes and HIGH for Motorola-type

addressing modes.

STRIP (Strip, Input, TTL)

STRIP is the overrulling signal which means that if STRIP is

continuously kept HIGH, the assertion of STOP STRIP or the

reception of a void frame or token doesn't enable the signalling

and learning features of the MU9C8248.

STOP STRIP (Stop Strip, Input, TTL)

When STOP STRIP has been asserted for one MCLK period

after STRIP has been HIGH for at least one MCLK period (and

STRIP is LOW now), the MU9C8248 stops stripping and

enables signalling and learning for the next FDDI frame.

MCLK (Master Clock, Input, TTL)

MCLK is the 25 MHz master clock. MCLK is used to clock all

system parts of the MU9C8248.

When STRIP has been asserted HIGH for only one MCLK

period and STOP STRIP is kept LOW, the MU9C8248 stops

the execution of the Routines 0 and 1 for the next FDDI frame.

The result is that no signalling on the MAC interface and SA

learning takes place. After STOP STRIP has been asserted for

one MCLK period or any token or void frame has been

received, signalling and learning is enabled again for the next

FDDI frame.

VCC, GND (Positive Power Supply and Ground)

These pins are the main power supply connections to the

MU9C8148. VCC must be held at +5V ± 10% relative to the

GND pin, which is at 0V (system reference potential), for

correct operation of the device.

FUNCTIONAL DESCRIPTION

Referring to the Block diagram shown on Page 1, the

MU9C8248 consists of four functional blocks: the Transparent

Bridging Block (TBB) , the Source Routing Block (SRB), the

Instruction/Data Buffer (IB), and the Arbiter. Five interfaces

connect the MU9C8248 to the FDDI Physical Layer device, the

MAC controller or System interface, the Host processor, an

external FIFO and the LANCAM. For a detailed description of

FDDI frames, refer to the ISO9314-2 Standard.

Transparent Bridging Block

For all frames which do not contain a Routing Information Field

(RIF), the TBB makes decisions whether to copy or discard a

frame based on the Destination address (DA) and the Frame

Control field (FC). If the MU9C8248 is not used in a

Transparent Bridging Only mode and a frame containing an

RIF is received the Source Routing Block performs the filtering

actions and no DA comparison takes place. If the bridge is set

for Transparent Bridging Only (the TBO bit in the Control

register is HIGH), the TBB also makes copy or discard

decisions (based on DA and/or FC) for frames which do contain

an RIF.

The TBB parses the data as received from the Physical Layer

device off the FDDI network, and indicates to the MAC

interface whether to assert the XDAMAT, XSAMAT, ABORT

and CIP signals. For each frame, the TBB examines the Frame

Control field (FC), the Destination address (DA), and the

Source address (SA), which contains the Routing Information

indicator (RII). If this RII is HIGH that frame contains a RIF.

The FC field indicates whether the current frame is a Token or

a regular frame. If a Token (Restricted or Non Restricted) is

being received the TBB discards it, thereby having the 8248 not

asserting any signals on the MAC interface. For a regular

frame, the bits in the Frame Control field signify the type of

frame (VOID, SMT, LLC, MAC, or Reserved) being received.

The TBB decides either to copy or discard the frame directly,

based on the settings in the Frame Type Selection register or

to filter on the DA.

Positive or negative filtering on the DA is selected by the

PONNE bit in the Transparent Bridging/MAC register. Filtering

on the DA is done on all frames except for VOID-, SMT- and

other types of frames with 16-bit addresses. No filtering and

signalling takes place for these frames.

Positive filtering implies that a frame should be forwarded if its

DA is found in the LANCAM address database. Routine 0 in the

instruction buffer examines the DA to determine whether a

frame should be copied or not. The results of this comparison

are used to notify the FDDI chip set to copy or discard the

frame. Negative filtering implies that a frame should be

forwarded if its DA is not found in the address database. In this

case, the MU9C8248 checks the DA and destinguishes

between MAC, Broadcast, Functional and Group addresses.

Based upon the settings of the Transparent Bridging/MAC

register, the TBB discards a frame whose DA is either a

Broadcast, Functional and/or Group address.

Rev. 2.5 Web

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