MU9C8248QEC Просмотр технического описания (PDF) - Music Semiconductors

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MU9C8248QEC

FDDI SRT Interface

Music Semiconductors 

MU9C8248

PIN DESCRIPTIONS (CONT’D)

Host Processor Interface:

ALE, SRNW (Address Latch Enable/System Read

Not Write, Input, TTL)

/RS, /WS, or /LDS and /UDS HIGH, the MU9C8248 takes

/HBRDY HIGH. /HBRDY becomes three-state one MCLK

period later.

/HBEN (Data Buffer Enable, Output, TTL)

This pin is ALE when the MU9C8248 is used in the Intel mode.

A positive pulse on ALE latches the address from the

multiplexed data/address lines. If the MU9C8248 is in the

Motorola mode, this pin becomes SRNW, and is HIGH for a

Host Processor Read cycle and LOW for a Write cycle.

If external bi-directional buffers are needed on the D15–D0

lines, /HBEN goes LOW to enable the external buffers. /HBEN

goes HIGH to disable the external buffers.

/HBDIR (Data Buffer Direction, Output, TTL)

/CS (Chip Select, Input, TTL)

/CS going LOW enables the Host Processor interface of the

MU9C8248 for a Host Processor read or write. When /CS is

HIGH, the Host Processor interface is not active.

A5–A0 (Address, Input, TTL)

The Address pins select the internal register for Host processor

reads and writes. Depending on the Processor interface, the

Address pins are latched by a positive pulse on ALE, or must

remain stable until the rising edge of /RS, /WS, or /LDS and

/UDS, as shown in the Timing diagrams.

/HBDIR controls the direction of external bi-directional buffers.

/HBDIR goes LOW to read from the registers of the MU9C8248

and HIGH to write to the MU9C8248 registers.

External FIFO Interface:

DF7-DF0 (FIFO data, Output, TTL)

On the rising edge of /WF, DF7-DF0 contain a part of a new

Source Address (SA), which is just learned by the LANCAM.

This new SA is written into an external FIFO connected to

these DF7-DF0 in six cycles.

D15–D0 (Data, Common I/O, TTL)

DFC (FIFO Control data, Output, TTL)

The Data pins transfer data between the Host Processor and

the internal registers of the MU9C8248. Depending on the

Processor Interface, the data pins are registered on the rising

edge of /WS, or /LDS and /UDS; or must remain stable until the

rising edge of /RS, or /LDS and /UDS, as shown in the Timing

diagrams.

On the rising edge of /WF, DFC indicates whether the part of

the new SA present on DF7-DF0 is the first part of this SA. If

this is the first of the six write cycles DFC is HIGH. For the

other five cycles, DFC is LOW.

/WF (FIFO Write, Output, TTL)

/RS, /LDS

(Read Strobe/Lower Data Strobe,

Input, TTL)

On the rising edge of /WF, data on DF7-DF0 and DFC is

present and can be written to e.g. an external FIFO.

If the MU9C8248 is used in the Intel mode, this pin is /RS and

goes LOW to begin a read cycle to the Host Processor

interface. If the MU9C8248 is used in the Motorola mode, this

pin is /LDS for Host processor read and write cycles and should

be asserted in combination with /UDS. Data is read by the Host

processor on the rising edge of /RS or /LDS, or is written into

the MU9C8248 on the rising edge of /LDS.

/FFI (FIFO Full, Input, TTL)

When /FFI is LOW, the MU9C8248 is indicated that the

external FIFO is full and can't accept new SAs. Learning of new

SAs in the LANCAM is then also disabled. When /FFI is HIGH

learning of new SAs both in the external FIFO and LANCAM is

enabled.

/WS, /UDS (Write Strobe/Upper Data Strobe,

Input, TTL)

If the MU9C8248 is used in the Intel mode, this pin is /WS, and

goes LOW to begin a write cycle from the Host Processor

interface. If the MU9C8248 is used in the Motorola mode, this

pin is /UDS for Host processor read and write actions and

should be asserted in combination with /LDS. Data is written

into the MU9C8248 on the rising edge of /WS or /UDS, or is

read from the MU9C8248 on the rising edge of /UDS.

/HBRDY (Ready, Output, Three-state TTL)

/HBRDY goes LOW to indicate to the Host processor that a

data transfer is completed. After the Host processor has made

Miscellaneous:

/RESET (Hardware Reset, Input, TTL)

Taking /RESET LOW for at least 1 MCLK cycle sets the

MU9C8248 to a predefined state. The contents of all registers

are 0000H after a Hardware reset.

/INT (Interrupt, Output, Open Drain)

This pin goes LOW to notify the Host processor that the

MU9C8248 is accessing the LANCAM. /INT is synchronized on

/HBRDY and becomes active directly if no Host Processor

LANCAM access cycle is active or after a possible pending

Host Processor LANCAM access cycle has been completed

(/HBRDY is HIGH) succesfully.

Rev. 2.5 Web

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