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ADCMP565BPZ Просмотр технического описания (PDF) - Analog Devices

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производитель
ADCMP565BPZ
ADI
Analog Devices ADI
ADCMP565BPZ Datasheet PDF : 16 Pages
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ADCMP565
TIMING INFORMATION
LATCH ENABLE
LATCH ENABLE
tS
tPL
tH
50%
DIFFERENTIAL
VIN
INPUT VOLTAGE
VOD
VREF ± VOS
Q OUTPUT
tPDL
tPLOH
tPDH
tF
Q OUTPUT
tPLOL
tR
Figure 3. System Timing Diagram
The timing diagram in Figure 3 shows the ADCMP565 compare
and latch features. Table 4 describes the terms in the diagram.
Table 4. Timing Descriptions
Symbol Timing
Description
tPDH
Input to output Propagation delay measured from
high delay
the time the input signal crosses
the reference (± the input offset
voltage) to the 50% point of an
output low-to-high transition
tPDL
Input to output Propagation delay measured from
low delay
the time the input signal crosses
the reference (± the input offset
voltage) to the 50% point of an
output high-to-low transition
tPLOH
Latch enable Propagation delay measured from
to output high the 50% point of the Latch Enable
delay
signal low-to-high transition to
the 50% point of an output low-
to-high transition
tPLOL
Latch enable
Propagation delay measured from
to output low the 50% point of the Latch Enable
delay
signal low-to-high transition to
the 50% point of an output high-
to-low transition
Symbol Timing
tH
Minimum
hold time
tPL
Minimum
latch enable
pulse width
tS
Minimum
setup time
tR
Output rise
time
tF
Output fall
time
VOD
Voltage
overdrive
50%
50%
02820-0-003
Description
Minimum time after the negative
transition of the Latch Enable
signal that the input signal must
remain unchanged to be acquired
and held at the outputs
Minimum time that the Latch
Enable signal must be high to
acquire an input signal change
Minimum time before the
negative transition of the Latch
Enable signal that an input signal
change must be present to be
acquired and held at the outputs
Amount of time required to
transition from a low to a high
output as measured at the 20%
and 80% points
Amount of time required to
transition from a high to a low
output as measured at the 20%
and 80% points
Difference between the
differential input and reference
input voltages
Rev. 0 | Page 8 of 16

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