ADCMP395ARMZ Просмотр технического описания (PDF) - Analog Devices

Номер в каталоге

Компоненты Описание

производитель

ADCMP395ARMZ

Single/Dual/Quad Comparators with Accurate Reference Output

Analog Devices 

Data Sheet

THEORY OF OPERATION

BASIC COMPARATOR

In its most basic configuration, a comparator can be used to

convert an analog input signal to a digital output signal (see

Figure 31). The analog signal on INx+ is compared to the

voltage on INx−, and the voltage at OUTx is either high or low,

depending on whether INx+ is at a higher or lower potential

than INx−, respectively.

VCC

V+

VIN

VREF

INx+

INx–

OUTx

VOUT

V+

VREF

0V

t

VIN

Figure 31. Basic Comparator and Input and Output Signals

RAIL-TO-RAIL INPUT (RRI)

Using a CMOS nonRRI stage (that is, a single differential pair)

limits the input voltage to approximately one gate-to-source

voltage (VGS) away from one of the supply lines. Because VGS

for normal operation is commonly more than 1 V, a single

differential pair input stage comparator greatly restricts the

allowable input voltage. This restriction can be quite limiting

with low voltage supplies. To resolve this issue, RRI stages allow

the input signal range to extend up to the supply voltage range.

In the case of the ADCMP394/ADCMP395/ADCMP396, the

inputs continue to operate 200 mV beyond the supply rails.

OPEN-DRAIN OUTPUT

The ADCMP394/ADCMP395/ADCMP396 have an open-drain

output stage that requires an external resistor to pull up to the

logic high voltage level when the output transistor is switched off.

The pull-up resistor must be large enough to avoid excessive

power dissipation, but small enough to switch logic levels

reasonably quickly when the comparator output is connected to

other digital circuitry. The rise time of the open-drain output

depends on the pull-up resistor (RPULLUP) and load capacitor (CL)

used.

The rise time can be calculated by

tR = 2.2 RPULLUP CL

(1)

ADCMP394/ADCMP395/ADCMP396

POWER-UP BEHAVIOR

On power-up, when VCC reaches 0.9 V, the ADCMP394/

ADCMP395/ADCMP396 is guaranteed to assert an output low

logic. When the voltage on the VCC pin exceeds UVLO, the

comparator inputs take control.

CROSSOVER BIAS POINT

Rail-to-rail inputs of this type of architecture in both op amps

and comparators, have a dual front-end design. PMOS devices

are inactive near the VCC rail, and NMOS devices are inactive near

GND. At some predetermined point in the common-mode range,

a crossover occurs. At this point, normally 0.8 V and VCC − 0.8 V,

the measured offset voltages change.

COMPARATOR HYSTERESIS

In noisy environments, or when the differential input amplitudes

are relatively small or slow moving, adding hysteresis (VHYST) to

the comparator is often desirable. The transfer function for a

comparator with hysteresis is shown in Figure 32. As the input

voltage approaches the threshold (0 V in Figure 32) from below

the threshold region in a positive direction, the comparator

switches from low to high when the input crosses +VHYST/2.

The new switch threshold becomes −VHYST/2. The comparator

remains in the high state until the −VHYST/2 threshold is crossed

from below the threshold region in a negative direction. In this

manner, noise or feedback output signals centered on the 0 V

input cannot cause the comparator to switch states unless it

exceeds the region bounded by ±VHYST/2.

OUTPUT

VOH

VOL

–VHYST

0V

2

+VHYSTINPUT

2

Figure 32. Comparator Hysteresis Transfer Function

Rev. B | Page 11 of 18

Share Link: