DatasheetQ Logo
Electronic component search and free download site. Transistors,MosFET ,Diode,Integrated circuits

ADAS1000-2 Просмотр технического описания (PDF) - Analog Devices

Номер в каталоге
Компоненты Описание
производитель
ADAS1000-2 Datasheet PDF : 85 Pages
First Prev 11 12 13 14 15 16 17 18 19 20 Next Last
Data Sheet
ADAS1000/ADAS1000-1/ADAS1000-2
TIMING CHARACTERISTICS
Standard Serial Interface
AVDD = 3.3 V ± 5%, IOVDD = 1.65 V to 3.6 V, AGND = DGND = 0 V, REFIN tied to REFOUT, externally supplied crystal/clock =
8.192 MHz. TA = −40°C to +85°C, unless otherwise noted. Typical specifications are mean values at TA = 25°C.
Table 5.
Parameter1
Output Rate2
IOVDD
3.3 V 2.5 V 1.8 V Unit
2
128
kHz
SCLK Cycle Time 25
tCSSA
8.5
tCSHA
3
tCH
8
tCL
8
tDO
8.5
11
tDS
2
tDH
2
tCSSD
2
tCSHD
2
tCSW
25
40
50
9.5
12
3
3
8
8
8
8
11.5
20
19
24
2
2
2
2
2
2
2
2
40
50
ns min
ns min
ns min
ns min
ns min
ns typ
ns max
ns min
ns min
ns min
ns min
ns min
tDRDY_CS2
0
0
0
ns min
tCSO
6
7
9
ns typ
RESET Low Time2 20
20
20
ns min
Description
Across specified IOVDD supply range; three programmable output data
rates available as configured in FRMCTL register (see Table 37) 2 kHz,
16 kHz, 128 kHz; use skip mode for slower rates
See Table 21 for details on SCLK vs. packet data rates
CS valid setup time to rising SCLK
CS valid hold time to rising SCLK
SCLK high time
SCLK low time
SCLK falling edge to SDO valid delay; SDO capacitance of 15 pF
SDI valid setup time from SCLK rising edge
SDI valid hold time from SCLK rising edge
CS valid setup time from SCLK rising edge
CS valid hold time from SCLK rising edge
CS high time between writes (if used). Note that CS is an optional input,
it may be tied permanently low. See a full description in the Serial
Interfaces section.
DRDY to CS setup time
Delay from CS assert to SDO active
Minimum pulse width; RESET is edge triggered
1 Guaranteed by characterization, not production tested.
2 Guaranteed by design, not production tested.
SCLK
CS
SDI
SDO
tCSHA
tCSSA
tCH tCL
tCSHD
tCSSD
MSB
DB[31]
tDS tDH
DB[30]
DB[29]
DB[25]
tCSW
DB[24]
DB[23]
DB[1]
DB[0]
LSB
tCSO
R/W
ADDRESS
DATA
MSB
DRDV DO_31LAST DO_30LAST
DO_29LAST
DO_25LAST
DO_1LAST
LSB
DO_0LAST
tDO
Figure 2. Data Read and Write Timing Diagram (CPHA = 1, CPOL = 1)
Rev. C | Page 11 of 85

Share Link: 

datasheetq.com  [ Privacy Policy ]Request Datasheet ] [ Contact Us ]