ADAS1000-4 Просмотр технического описания (PDF) - Analog Devices
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ADAS1000-4 Datasheet PDF : 80 Pages
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Data Sheet
ADAS1000-3/ADAS1000-4
TIMING CHARACTERISTICS
Standard Serial Interface
AVDD = 3.3 V ± 5%, IOVDD = 1.65 V to 3.6 V, AGND = DGND = 0 V, REFIN tied to REFOUT, externally supplied crystal/clock =
8.192 MHz. TA = −40°C to +85°C, unless otherwise noted. Typical specifications are mean values at TA = 25°C.
Table 5.
Parameter1
Output Rate2
IOVDD
3.3 V 2.5 V 1.8 V Unit
2
128
kHz
SCLK Cycle Time 25
tCSSA
8.5
tCSHA
3
tCH
8
tCL
8
tDO
8.5
11
tDS
2
tDH
2
tCSSD
2
tCSHD
2
tCSW
25
40
50
9.5
12
3
3
8
8
8
8
11.5
20
19
24
2
2
2
2
2
2
2
2
40
50
ns min
ns min
ns min
ns min
ns min
ns typ
ns max
ns min
ns min
ns min
ns min
ns min
tDRDY_CS2
0
0
0
ns min
tCSO
6
7
9
ns typ
RESETE Low Time2 20
20
20
ns min
A
A
Description
Across specified IOVDD supply range; three programmable output data
rates available as configured in FRMCTL register (see Table 37) 2 kHz,
16 kHz, 128 kHz; use skip mode for slower rates.
See Table 21 for details on SCLK frequency vs. packet data/frame rates.
CSE valid setup time to rising SCLK.
A
A
CSE valid hold time to rising SCLK.
A
A
SCLK high time.
SCLK low time.
SCLK falling edge to SDO valid delay; SDO capacitance of 15 pF.
SDI valid setup time from SCLK rising edge.
SDI valid hold time from SCLK rising edge.
CSE valid setup time from SCLK rising edge.
A
A
CSE valid hold time from SCLK rising edge.
A
A
CSE high time between writes (if used). Note that CSE is an optional input,
A
A
A
A
it may be tied permanently low. See a full description in the Serial
Interfaces section.
DRDYE to CSE setup time.
A
A
A
A
Delay from CSE assert to SDO active.
A
A
Minimum pulse width; RESETE is edge triggered.
A
A
1 Guaranteed by characterization, not production tested.
2 Guaranteed by design, not production tested.
SCLK
CS
SDI
SDO
tCSHA
tCSSA
tCH tCL
tCSHD
tCSSD
MSB
DB[31]
tDS tDH
DB[30]
DB[29]
DB[25]
tCSW
DB[24]
DB[23]
DB[1]
DB[0]
LSB
tCSO
R/W
MSB
DRDY
DO_31
DO_30
ADDRESS
DO_29
DO_25
DATA
DO_1
LSB
DO_0
tDO
Figure 2. Data Read and Write Timing Diagram (CPHA = 1, CPOL = 1)
Rev. B | Page 11 of 80
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