AD7703ANZ Просмотр технического описания (PDF) - Analog Devices
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AD7703ANZ Datasheet PDF : 18 Pages
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AD7703
TIMING CHARACTERISTICS1, 2 (AVDD = DVDD = +5 V ؎ 10%; AVSS = DVSS = –5 V ؎ 10%; AGND = DGND = O V;
fCLKIN = 4.096 MHz; Input Levels: Logic O = O V, Logic 1 = DVDD; unless otherwise noted.)
Parameter
Limit at TMIN, TMAX Limit at TMIN, TMAX
(A, B Versions)
(S, T Versions) Unit
Conditions/Comments
fCLKIN3, 4
tr5
tf5
t1
t2
t36
200
5
200
5
50
50
0
50
1000
200
5
200
5
50
50
0
50
1000
kHz min
MHz max
kHz min
MHz max
ns max
ns max
ns min
ns min
ns min
Master Clock Frequency: Internal Gate Oscillator
Typically 4.096 MHz
Master Clock Frequency: Externally Supplied
Digital Output Rise Time. Typically 20 ns.
Digital Output Fall Time. Typically 20 ns.
SC1, SC2 to CAL High Setup Time
SC1, SC2 Hold Time after CAL Goes High
SLEEP High to CLKIN High Setup Time
SSC MODE
t47
t5
t6
7
t8
t98
t108, 9
3/fCLKIN
100
250
300
790
l/fCLKIN + 200
4/fCLKIN + 200
3/fCLKIN
100
250
300
790
l/fCLKIN + 200
4/fCLKIN + 200
ns max
ns max
ns min
ns max
ns max
ns max
ns max
Data Access Time (CS Low to Data Valid)
SCLK Falling Edge to Data Valid Delay (25 ns typ)
MSB Data Setup Time. Typically 380 ns.
SCLK High Pulsewidth. Typically 240 ns.
SCLK Low Pulsewidth. Typically 730 ns.
SCLK Rising Edge to Hi-Z Delay (l/fCLKIN + 100 ns typ)
CS High to Hi-Z Delay
SEC MODE
fSCLK
5
t11
35
t12
160
t137, 10
160
t1411
150
t158
250
t168
200
5
MHz max Serial Clock Input Frequency
35
ns min SCLK Input High Pulsewidth
160
ns min SCLK Low Pulsewidth
160
ns max Data Access Time (CS Low to Data Valid). Typically 80 ns.
150
ns max SCLK Falling Edge to Data Valid Delay. Typically 75 ns.
250
ns max CS High to Hi-Z Delay
200
ns max SCLK Falling Edge to Hi-Z Delay. Typically 100 ns.
NOTES
1Sample tested at 25°C to ensure compliance. All input signals are specified with t r = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.
2See Figures 1 to 6.
3CLKIN duty cycle range is 20% to 80%. CLKIN must be supplied whenever the AD7703 is not in SLEEP mode. If no clock is present in this case, the device
can draw higher current than specified and possibly become uncalibrated.
4The AD7703 is production tested with fCLKIN at 4.096 MHz. It is guaranteed by characterization to operate at 200 kHz.
5Specified using 10% and 90% points on waveform of interest.
6In order to synchronize several AD7703s together using the SLEEP pin, this specification must be met.
7t4 and t13 are measured with the load circuit of Figure 1 and defined as the time required for an output to cross 0.8 V or 2.4 V.
8t9, t10, t15, and t16 are derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number
is then extrapolated back to remove the effects of charging or discharging the 100 pF capacitor. This means that the time quoted in the Timing Characteristics is
the true bus relinquish time of the part and as such is independent of external bus loading capacitance.
9If CS is returned high before all 20 bits are output, the SDATA and SCLK outputs will complete the current data bit and then go to high impedance.
10If CS is activated asynchronously to DRDY, CS will not be recognized if it occurs when DRDY is high for four clock cycles. The propagation delay time may be
as great as four CLKIN cycles plus 160 ns. To guarantee proper clocking of SDATA when using asynchronous CS, the SCLK input should not be taken high
sooner than four CLKIN cycles plus 160 ns after CS goes low.
11SDATA is clocked out on the falling edge of the SCLK input.
Specifications subject to change without notice.
IOL
1.6mA
TO
OUTPUT
PIN CL
100pF
+2.1V
IOH
200A
Figure 1. Load Circuit for Access Time
and Bus Relinquish Time
–4–
CAL
SC1, SC2
t1
t2
SC1, SC2 VALID
Figure 2. Calibration Control Timing
CLKIN
t3
SLEEP
Figure 3. Sleep Mode Timing
REV. F
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