AD5341(Rev0) Просмотр технического описания (PDF) - Analog Devices
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Компоненты Описание
производитель
AD5341
(Rev.:Rev0)
(Rev.:Rev0)
Analog Devices
AD5341 Datasheet PDF : 20 Pages
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BUF
GAIN
DB.. 7
DB0
CS
WR
CLR
LDAC
AD5330 FUNCTIONAL BLOCK DIAGRAM
AD5330/AD5331/AD5340/AD5341
AD5330 PIN CONFIGURATION
POWER-ON
RESET
VREF
VDD
AD5330
INTER-
FACE
LOGIC
INPUT
REGISTER
DAC
REGISTER
8-BIT
DAC
BUFFER
VOUT
RESET
POWER-DOWN
LOGIC
BUF 1
20 DB7
NC 2
19 DB6
VREF 3
18 DB5
VOUT
GND
CS
WR
4
17 DB4
8-BIT
5 AD5330 16 DB3
6
TOP VIEW 15
(Not to Scale)
DB2
7
14 DB1
GAIN 8
13 DB0
CLR 9
12 VDD
LDAC 10
11 PD
NC = NO CONNECT
PD GND
Pin
No.
1
2
3
4
5
6
7
8
9
10
11
12
13–20
Mnemonic
BUF
NC
VREF
VOUT
GND
CS
WR
GAIN
CLR
LDAC
PD
VDD
DB0–DB7
AD5330 PIN FUNCTION DESCRIPTIONS
Function
Buffer Control Pin. This pin controls whether the reference input to the DAC is buffered or unbuffered.
No Connect.
Reference Input.
Output of DAC. Buffered output with rail-to-rail operation.
Ground reference point for all circuitry on the part.
Active Low Chip Select Input. This is used in conjunction with WR to write data to the parallel interface.
Active Low Write Input. This is used in conjunction with CS to write data to the parallel interface.
Gain Control Pin. This controls whether the output range from the DAC is 0–VREF or 0–2 VREF.
Asynchronous active low control input that clears all input registers and DAC registers to zero.
Active low control input that updates the DAC registers with the contents of the input registers.
Power-Down Pin. This active low control pin puts the DAC into power-down mode.
Power Supply Input. These parts can operate from 2.5 V to 5.5 V and the supply should be decoupled
with a 10 µF capacitor in parallel with a 0.1 µF capacitor to GND.
Eight Parallel Data Inputs. DB7 is the MSB of these eight bits.
REV. 0
–5–
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