MR20H40VDC Просмотр технического описания (PDF) - Extech Instruments Corporation.
Номер в каталоге
Компоненты Описание
производитель
MR20H40VDC Datasheet PDF : 28 Pages
| |||
MR20H40 / MR25H40
Write Disable (WRDI)
The Write Disable (WRDI) command resets the Write Enable Latch (WEL) bit in the status register (bit 7) to 0.
This prevents writes to status register or memory. The WRDI command is entered by driving CS low, sending
the command code, and then driving CS high.
The Write Enable Latch (WEL) is reset to 0 on power-up or when the WRDI command is completed.
Figure 6 – Write Disable (WRDI) Timing
CS
SCK
Mode 3
Mode 0
0
1
2
3
4
5
6
7
Instruction (04h)
Mode 3
Mode 0
SI
0
0
0
0
0
1
0
0
SO
High Impedance
Write Status Register (WRSR)
The Write Status Register (WRSR) command allows new values to be written to the Status Register. The
WRSR command is not executed unless the Write Enable Latch (WEL) has been set to 1 by executing a WREN
command while pin WP and bit SRWD correspond to values that make the status register writable as seen in
Table 4 on page 8. Status Register bits are non-volatile with the exception of the WEL which is reset to 0
upon power cycling.
The WRSR command is entered by driving CS low, sending the command code and status register write data
byte, and then driving CS high.
Figure 7 – Write Status Register (WRSR) Timing
CS
SCK
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Mode 3
Mode 0
Instruction (01h)
Status Register In
SI
0000000176543210
MSB
SO
High Impedance
Copyright © Everspin Technologies 2014
10
MR20H40 / MR25H40 Revision 11, 8/2014
Share Link: 