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74LVC821AD,112

10-bit D-type flip-flop with 5 V tolerant inputs/outputs; positive-edge trigger; 3-state

NXP Semiconductors. 

NXP Semiconductors

11. Waveforms

74LVC821A

10-bit D-type flip-flop; 5 V tolerance; positive-edge trigger; 3-state

VI

CP input

GND

VOH

Qn output

VOL

1/fmax

VM

tW

t PHL

VM

t PLH

mna894

Fig 7.

Measurement points are given in Table 8.

VOL and VOH are the typical output voltage levels that occur with the output load.

Clock (CP) to output (Qn) propagation delays, the clock pulse width, and the maximum frequency

CP input

VI

GND

Dn input

VI

GND

VM

tsu

th

VM

tsu

th

Qn output

VOH

VOL

VM

mna202

Fig 8.

Measurement points are given in Table 8.

VOL and VOH are the typical output voltage levels that occur with the output load.

The shaded areas indicate when the input is permitted to change for predicable output performance.

Data set-up and hold times for the Dn input to the CP input

74LVC821A

Product data sheet

All information provided in this document is subject to legal disclaimers.

Rev. 4 — 23 November 2012

© NXP B.V. 2012. All rights reserved.

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