74AHC86D-Q100 Просмотр технического описания (PDF) - NXP Semiconductors.
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74AHC86D-Q100 Datasheet PDF : 15 Pages
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Nexperia
74AHC86-Q100; 74AHCT86-Q100
Quad 2-input EXCLUSIVE-OR gate
5. Pinning information
5.1 Pinning
$+&4
$+&74
$
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$
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*1'
9&&
%
$
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DDD
Fig 4. Pin configuration SO14, TSSOP14
5.2 Pin description
Table 2.
Symbol
1A to 4A
1B to 4B
1Y to 4Y
GND
VCC
Pin description
Pin
1, 4, 9, 12
2, 5, 10, 13
3, 6, 8, 11
7
14
Description
data input
data input
data outputs
ground (0 V)
supply voltage
6. Functional description
Table 3. Function table[1]
Input nA
L
L
H
H
[1] H = HIGH voltage level;
L = LOW voltage level.
Input nB
L
H
L
H
WHUPLQDO
LQGH[DUHD
$+&4
$+&74
%
<
$
%
<
*1'
%
$
<
%
$
DDD
7UDQVSDUHQWWRSYLHZ
(1) This is not a supply pin. The substrate is attached to this
pad using conductive die attach material. There is no
electrical or mechanical requirement to solder this pad.
However, if it is soldered, the solder land should remain
floating or be connected to GND.
Fig 5. Pin configuration DHVQFN14
Output nY
L
H
H
L
74AHC_AHCT86_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 5 June 2013
© Nexperia B.V. 2017. All rights reserved
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