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5962-8863401UC

5V, Byte Alterable EEPROM

Intersil 

Pinouts

X28HC256

(28 LD FLATPACK, PDIP, SOIC)

TOP VIEW

A14 1

28 VCC

A12

2

27 WE

A7 3

26 A13

A6 4

25 A8

A5 5

24 A9

A4 6

23 A11

A3

7

22

X28HC256

OE

A2 8

21 A10

A1 9

20 CE

A0 10

19 I/O7

I/O0 11

18 I/O6

I/O1 12

17 I/O5

I/O2 13

16 I/O4

VSS 14

15 I/O3

X28HC256

X28HC256

(32 LD PLCC, LCC)

TOP VIEW

4 3 2 1 32 31 30

A6 5

29 A8

A5 6

28 A9

A4 7

27 A11

A3 8

A2 9

X28HC256

26 NC

25 OE

A1 10

24 A10

A0 11

23 CE

NC 12

22 I/O7

I/O0 13

21 I/O6

14 15 16 17 18 19 20

Pin Descriptions

Addresses (A0 to A14)

The Address inputs select an 8-bit memory location during a

read or write operation.

Chip Enable (CE)

The Chip Enable input must be LOW to enable all read/write

operations. When CE is HIGH, power consumption is

reduced.

Output Enable (OE)

The Output Enable input controls the data output buffers,

and is used to initiate read operations.

Data In/Data Out (I/O0 to I/O7)

Data is written to or read from the X28HC256 through the I/O

pins.

Write Enable (WE)

The Write Enable input controls the writing of data to the

X28HC256.

Pin Names

SYMBOL

A0 to A14

I/O0 to I/O7

WE

CE

OE

VCC

VSS

NC

DESCRIPTION

Address Inputs

Data Input/Output

Write Enable

Chip Enable

Output Enable

+5V

Ground

No Connect

Device Operation

Read

Read operations are initiated by both OE and CE LOW. The

read operation is terminated by either CE or OE returning

HIGH. This two line control architecture eliminates bus

contention in a system environment. The data bus will be in

a high impedance state when either OE or CE is HIGH.

Write

Write operations are initiated when both CE and WE are

LOW and OE is HIGH. The X28HC256 supports both a CE

and WE controlled write cycle. That is, the address is latched

by the falling edge of either CE or WE, whichever occurs

last. Similarly, the data is latched internally by the rising edge

of either CE or WE, whichever occurs first. A byte write

operation, once initiated, will automatically continue to

completion, typically within 3ms.

3

FN8108.3

September 21, 2011

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