56F8123 Просмотр технического описания (PDF) - Freescale Semiconductor

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56F8123

16-bit Digital Signal Controllers

Freescale Semiconductor 

56F8323/56F8123 Features

Part 1 Overview

1.1 56F8323/56F8123 Features

1.1.1 Core

• Efficient 16-bit 56800E family engine with dual Harvard architecture

• Up to 60 Million Instructions Per Second (MIPS) at 60MHz core frequency

• Single-cycle 16 × 16-bit parallel Multiplier-Accumulator (MAC)

• Four 36-bit accumulators, including extension bits

• Arithmetic and logic multi-bit shifter

• Parallel instruction set with unique addressing modes

• Hardware DO and REP loops

• Three internal address buses

• Four internal data buses

• Instruction set supports both DSP and controller functions

• Controller-style addressing modes and instructions for compact code

• Efficient C compiler and local variable support

• Software subroutine and interrupt stack with depth limited only by memory

• JTAG/EOnCE debug programming interface

1.1.2 Differences Between Devices

Table 1-1 outlines the key differences between the 56F8323 and 56F8123 devices.

Feature

Guaranteed Speed

Program RAM

Data Flash

PWM

CAN

Quadrature Decoder

Temperature Sensor

Dedicated GPIO

Table 1-1 Device Differences

56F8323

60MHz/60 MIPS

4KB

8KB

1x6

1

1x4

1

—

56F8123

40MHz/40 MIPS

Not Available

Not Available

Not Available

Not Available

Not Available

Not Available

10

56F8323 Technical Data, Rev. 17

Freescale Semiconductor

7

Preliminary

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