LC824204-13YB Просмотр технического описания (PDF) - ON Semiconductor
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LC824204-13YB Datasheet PDF : 14 Pages
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*I2Cbus timing
SCL
SDA
LC824204-13YB
tF
tHIGH
tLOW
tSU.STA
tHD.STA tHD.DAT
tSU.DAT
tR
tSP
tSU.STO
tSP
tBUF
Symbol
Parameter
Min
tSCL
SCL clock fr.
0
tBUF
Bus release period
1.3
tHD:STA
Hold time (Start)
0.6
tLOW
SCL_Lo period
1.3
tHIGH
SCL_Hi period
0.6
tR
Rise time
tF
Fall time
tSU:STA
Setup time (Start)
0.6
tSU:STO
Setup time (Stop)
0.6
tSU:DAT
Setup time (Data)
100
tHD:DAT
Hold time (Data)
0
tSP
Removable spike
width
Max
Unit
400
kHz
μs
μs
μs
μs
300
ns
300
ns
μs
μs
ns
ns
50
ns
I2C system reset
RESETB
tRSTL
*2)
VDD
Symbol
Parameter
Min
tRSTL * 1)
resetLow time
5
Max
Unit
μs
* 1) RESETB is the reset signal of the group of register by I2C. Therefore, you need Low
period for tRSTL after powering VDD.
No.A2221-11/14
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