M5M51008DFP Просмотр технического описания (PDF) - MITSUBISHI ELECTRIC
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M5M51008DFP Datasheet PDF : 8 Pages
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Write cycle ( S1 control mode)
A0~16
S1
Ver. 1.1
MITSUBISHI LSIs
M5M51008DFP,VP,RV,KV,KR -55H, -70H
1048576-BIT(131072-WORD BY 8-BIT)CMOS STATIC RAM
tCW
tsu (A)
tsu (S1)
trec (W)
S2
(Note 3)
(Note 5)
W
(Note 3)
DQ1~8
Write cycle (S2 control mode)
A0~16
(Note 4)
tsu (D)
th (D)
DATA IN
STABLE
tCW
(Note 3)
(Note 3)
S1
S2
W
DQ1~8
(Note 3)
tsu (A)
tsu (S2)
trec (W)
(Note 3)
(Note 5)
(Note 3)
(Note 4)
tsu (D)
th (D)
DATA IN
STABLE
Note 3: Hatching indicates the state is "don't care".
4: Writing is executed while S2 high overlaps S1 and W low.
5: When the falling edge of W is simultaneously or prior to the falling edge of S1
or rising edge of S2, the outputs are maintained in the high impedance state.
6: Don't apply inverted phase signal externally when DQ pin is output mode.
(Note 3)
MITSUBISHI
ELECTRIC
6
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