HIP5020 Просмотр технического описания (PDF) - Intersil

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HIP5020

Integrated-Power Buck Converter Controller with Synchronous Rectification

Intersil 

HIP5020

Electrical Specifications VfroINm=06o.C3VtoDC12, 5CooCm; pUonnleesnstsOrethfeerrewnisceedSfproemcifiFeidgu(rCeo1n. tTinYuPevda)lues at TJ = 25oC and MIN, MAX limits are for TJ

PARAMETER

SYMBOL

TEST CONDITIONS

2T5Jo=C

TYP

0oC < TJ < 125oC

MIN

MAX

UNITS

ERROR AMPLIFIER

Internal Integration Capacitor

12

-

-

pF

Open-Loop Voltage Gain

AV

89

-

-

dB

Gain-Bandwidth Product

GBW

7.2

-

-

MHz

Input Bias Current

SOFT START

IFB

VFB = 1.26VDC

3

-70

70

nA

Current Source

OSCILLATOR

ISOFT

10

6

14

µA

CT Charging Current

126

110

140

µA

Initial Frequency Accuracy

±3

-

-

%

Total Frequency Variation

PROTECTIVE FUNCTION

VIN = 4.5 to 18V

±7

-

±10

%

Current Limit Threshold

PWM MODULATOR

IO PK

4.5

4

-

A

Modulator Gain

1.7

-

-

A/V

Minimum On Time

100

-

-

ns

Minimum Off Time

115

-

-

ns

HYSTERETIC COMPARATOR

Propagation Delay

SLOPE GENERATOR

Step VFB

3

-

-

µs

Slope Capacitor Charge Current

ISLOPE

80

-

-

µA

Example Application Guide

The HIP5020 provides the flexibility to meet differing needs.

This section illustrates the trade-off of component selection

for three DC-DC converter circuit designs. Each circuit is

optimized for a specific goal: Circuit 1 is optimized for high

efficiency, Circuit 2 is optimized for small size, and Circuit 3

is optimized for low cost. Figure 1 shows the schematic

common to all three converter designs. Table 1 shows the

expected performance parameters for each circuit. Table 2

gives the value of each component referenced in Figure 1.

Table 3 provides a listing of suggested vendors for the major

(or critical) components. Figures 2, 3 and 4 show the

efficiency and transient performance of each circuit.

2-16

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