HIP5020 Просмотр технического описания (PDF) - Intersil
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HIP5020 Datasheet PDF : 15 Pages
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HIP5020
Using the built-in 12pF integration capacitor across the error
amplifier, the transfer function, G(s) for the lead-lag network is:
G(s) = K-s-- • 1-1----++-----ss-----⁄⁄--ωω-----pz-
where K = R-----1-----•----1----2--1---•----1---0----–---1---2-
ωz = (---R-----1-----+-----R--1--6----)----•----C-----9-
and ωp = R-----6-----1•----C-----9--
The HIP5020 design and simulation software (available at
the Harris WEB site) computes these values and greatly
simplifies the following compensation design process. To
design a DC-DC converter for stable operation:
1. Determine the output capacitor’s ESR zero frequency,
fESR which is given by: 1 ⁄ (2 • π • C1 • ESR)
2. Place the compensation pole (ωp/2π) at the ESR zero fre-
quency, fESR.
3. Determine the desired converter bandwidth (or the fre-
quency where the loop gain is unity). Bandwidth must be
below 1/2 the switching frequency. A reasonable band-
width is approximately 1/10 the switching frequency.
4. Select the compensation zero (ωz) well below the desired
bandwidth frequency and adjust as necessary to achieve
the desired phase margin (40o Minimum).
5. Adjust the gain (via R1) and iterate the compensation zero
and gain as needed to achieve the desired bandwidth
and phase margin.
6. Measure the closed-loop transfer function at both mini-
mum and maximum input voltage and at both full load
and the Run-to-Hysteretic mode load current boundary.
Be sure to note the phase margin and the gain margin.
The single component R1 can compensate the control loop if
the detailed characteristics of the output capacitor, bandwidth,
and switching frequency meet strict requirements. The
bandwidth (or unity gain frequency) must be much greater
than the ESR zero frequency (fESR) and much less than twice
the switching frequency. Additionally the break frequency of
output capacitor’s ESL must be much greater than the
switching frequency. If these conditions exist, the ESR zero
provides the necessary phase boost. However, note that the
ESR is not a well controlled parameter and is variable with
temperature and aging. Select R1 for the proper
compensation gain and confirm the selection with closed-loop
measurements. Additionally determine the worst case ESR
variation and estimate this effect on converter stability.
Output Voltage Setting
The resistor divider R1 and R2 sets the output voltage as a
function of the reference voltage. Select R1 to achieve the
desired bandwidth then determine R2 from:
R2
=
R
1
•
--------1---.--2---6---------
VO – 1.26
The output voltage regulation improves with the use of
integrated resistor network. By integrating the resistors, the
variations of R1 track the variations of R2. The ratio of R1 to
R2 remains constant and this minimizes the output voltage
variation to improve regulation. Integrated resistor networks
are available in small SOT-23 packages such as the one
used in Circuit 2.
Slope Compensation
Slope compensation is necessary to avoid current loop
instability for duty ratios above 50%. Select C7 to set the
amount of slope compensation according to the following:
C7MAX = L----1-----•----2----7V---2-O----•----1----0---–---6-
This value of capacitance provides a compensation ramp that is
1/2 of the reflected output inductor decreasing current slope.
Charge Pump and Bootstrap Design
The charge pump and bootstrap circuit supply the internal
bias power for the HIP5020. The majority of the bias power
goes to gate drives. The charge pump operates at the
switching frequency for input voltage below 9.8V. Select
capacitors C4 and C5 according to the following:
C4, C5MIN
=
-0---.--0---8---8--
FS
+
0.
12
•
10–6
The gate of the upper N-Channel MOSFET is driven above
the input voltage by the internal gate drive with power
supplied by the bootstrap circuit D1 and C3. A fast recovery,
low leakage diode is recommended for D1. C3 should be a
high quality ceramic capacitor.
Hysteretic Mode Current Setting
The voltage on the HMI pin sets the load current boundary
between Run mode and Hysteretic mode. This setting
enables the designer to trade-off efficiency and output
voltage ripple at low output current. The output voltage ripple
is higher in Hysteretic mode as compared with Run mode.
Many systems can tolerate higher power supply ripple at
light loads because the reduced load induced ripple. The
designer should select the load current boundary based
upon converter efficiency characteristics and known load
characteristics. For example, a HIP5020 converter powering
a microprocessor load might select the HMI boundary
between the sleep and active states of operation.
The ripple voltage is highest for load current just below the
mode boundary. The ripple voltage is a function of the
hysteresis width, the resistors R1 and R2, the hysteretic
current setting (HMI) and the output capacitor ESR as
described in the Hysteretic Mode section.
Figure 9 shows the efficiency versus load for two different
VHMI settings. The efficiency at light load current is higher
with a higher settings. The efficiency at light load current is
higher VHMI setting. However, the more efficient design has
2-23
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