82545GM Просмотр технического описания (PDF) - Intel

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производитель

82545GM

Gigabit Ethernet Controller

Intel 

Networking Silicon — 82545GM

4.2

4.2.1

Pins not included in XOR test tree:

• JTAG (TAP) interface: TRST_N, TCK, TDO, TMS, and TDO

• Test mode decode controls TEST_DM_N, EWRAP, CLK_BYP_N, CLK_VIEW, and

SDP_B[7]

• Each internal PHY's analog signals including PHYREF, MDI +/-, and PHY_HSDACP/N

• PCI Impedance Compensation ZPCOMP and ZNCOMP

• Oscillator signals XTAL1 and XTAL2

• Test signals including PHY_TSTPT and each PHY's HSDACP/N

• Power-control pins CTRL_15, CTRL_25_A, and CTRL_25_B

• SMB_ALERT_N/PCI_PWR_GOOD

Tristate Mode

The 82545GM's tristate test mode is used to explicitly disable output drivers and place outputs in

high-impedance (tristate) state. To more readily support XOR or NAND-tree like testing of other

system components, the 82545GM decodes this test mode from the same signal pins used to

exercise XOR tree testing. The 82545GM additionally supports a mechanism to enter tristate mode

via the IEEE 802.3 JTAG (TAP) controller.

Tristate Mode Control and Operation

The following signals are required to place the 82545GM in tristate test mode:

4.2.2

Test

Function/

Mode

Pin Name

Tristate

Mode

Dual-Mode

Name

TEST_DM_N

EWRAP

TEST_

MODE[3]

0

0

CLK_BYP_N CLK_VIEW SDP_B[7]

TEST_

MODE[2]

1

TEST_

MODE[1]

0

TEST_

MODE[0]

1

When in tristate test mode:

• All output drivers for all digital signal pins are disabled (with the exception of the TDO pin).

• Analog signals such as MDI+/-, analog test points, and regulator controls are unaffected.

Tristate Mode Using JTAG (TAP)

The 82545GM can also be placed in tristate mode using the JTAG interface and the HIGHZ

instruction.

The HIGHZ instruction is used to place the 82545GM in high-impedance (TRISTATE) mode,

where all digital signal outputs are placed in high-impedance (tri-state) output state.

Datasheet

21

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