EL7558BCM Просмотр технического описания (PDF) - Elantec -> Intersil

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EL7558BCM

Integrated Adjustable 8 Amp Synchronous Switcher

Elantec -> Intersil 

EL7558BC

Integrated Adjustable 8 Amp Synchronous Switcher

parator will terminate the high-side switch. If ILMAX

has not been reached, the regulator output voltage is then

compared to the reference voltage VREF. The resultant

error voltage is summed with the current feedback and

slope compensation ramp. The high-side switch remains

on until all three comparator inputs have summed to

zero, at which time the high-side switch is turned off and

the low-side switch is turned on. In order to eliminate

cross-conduction of the high-side and low-side switches

a 10ns break-before-make delay is incorporated in the

switch driver circuitry. In the continuous mode of opera-

tion the low-side switch will remain on until the end of

the oscillator period. In order to improve the low current

efficiency of the EL7558BC, a zero-crossing comparator

senses when the inductor transitions through zero. Turn-

ing off the low-side switch at zero inductor current

prevents forward conduction through the internal clamp-

ing diodes (LX to VSSP) when the low-side switch turns

off, reducing power dissipation. The output enable

(OUTEN) input allows the regulator output to be dis-

abled by an external logic control signal.

Output Voltage Mode Select

The VCC2DET multiplexes the FB1 and FB2 pins to the

PWM controller. A logic 1 on VCC2DET selects the

FB2 input and forces the output voltage to the internally

programmed value of 3.50V. A logic zero on VCC2DET

selects FB1 and allows the output to be programmed

from 1.0 to 3.8V. In general:

VOUT

=

1.0V

×





1

+

RR-----34

× Volt

However, due to the relatively low open loop gain of the

system, gain errors will occur as the output voltage and

loop-gain are changed. This is shown in the performance

curves. (The output voltage is factory trimmed to mini-

mize error at a 2.50V output). A 2µA pull-up current

from FB1 to VIN forces VOUT to GND in the event that

FB1 is not used and the VCC2DET is inadvertently tog-

gled between the internal and external feedback mode of

operation.

NMOS Power FETS and Drive Circuitry

The EL7558BC integrates low resistance (25mΩ)

NMOS FETS to achieve high efficiency at 8A. Gate

drive for both the high-side and low-side switches is

derived through a charge pump consisting of the CP pin

and external components D1-D3 and C5-C6. The CP

output is a low resistance inverter driven at one-half the

oscillator frequency. This is used in conjunction with

D2-D3 to generate a 7.5V (typical) voltage on the C2V

pin which provides gate drive to the low-side NMOS

switch and associated level shifter. In order to use an

NMOS switch for the high-side drive it is necessary to

drive the gate voltage above the source voltage (LX).

This is accomplished by boot-strapping the VHI pin

above the C2V voltage with capacitor C6 and diode D1.

When the low-side switch is turned on the LX voltage is

close to GND potential and capacitor C6 is charged

through diodes D1-D3 to approximately 6.9V. At the

beginning of the next cycle the high side switch turns on

and the LX pin begins to rise from GND to VDD poten-

tial. As the LX pin rises the positive plate of capacitor

C6 follows and eventually reaches a value of approxi-

mately 11.2V, for VDD=5V. This voltage is then level

shifted and used to drive the gate of the high-side FET,

via the VHI pin.

Reference

A 1% temperature compensated band gap reference is

integrated in the EL7558BC. The external CREF capac-

itor acts as the dominant pole of the amplifier and can be

increased in size to maximize transient noise rejection.

A value of 0.1uF is recommended.

Oscillator

The system clock is generated by an internal relaxation

oscillator with a maximum duty-cycle of approximately

96%. Operating frequency can be adjusted through the

COSC pin or can be driven by an external clock source.

If the oscillator is driven by an external source, care

must be taken in the selection of CSLOPE. Since the

COSC and CSLOPE values determine the open loop

gain of the system, changes to COSC require corre-

sponding changes to CSLOPE in order to maintain a

constant gain ratio. The recommended ratio of COSC to

CSLOPE is 1.5:1

Temperature Sensor

An internal temperature sensor continuously monitors

die temperature. In the event that die temperature

11

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