WM8144-10CFT/V Просмотр технического описания (PDF) - Wolfson Microelectronics plc

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WM8144-10CFT/V

Integrated 10-bit Data Acquisition system for Imaging Applications

Wolfson Microelectronics plc 

WM8144-10

Theory of Operation (contd.)

The position of the clamp relative to the video sample is

programmable by CDSREF1-0 (see Table 7). By default,

the reset sample occurs on the fourth MCLK rising edge

after VSMP. The relative timing between the reset sam-

ple ( and CL) and video sample can be altered as shown

in Figure 4.

Video Input

Clamp Pulse

Figure 5

A reset level clamp is activated if the RLC pin is high on

an MCLK rising edge (Figure 6). By default this initiates

an internal clamp pulse three MCLK pulses later (Figure

4: CL). The relationship between CL and RS is fixed.

Therefore altering the RS position also alters the CL po-

sition (Figure 4). Table 7 shows the three possible voltages

to which the reset level can be clamped.

Figure 4: Reset Sample and Clamp Timing

When the clamp pulse is active the voltage on the

WM8144-10 side of Cin, i.e. RINP, will be forced to be

equal to the VRLC clamp voltage (see Figure 5). The

VRLC clamp voltage is programmable to three different

levels via the serial interface (1.5V, 2.5V or 3.5V). The

voltage to which the clamp voltage should be programmed

is dependent on the type of sampling selected and the

polarity of the input video signal. For CDS operation it is

important to match the clamp voltage to the amplitude

and polarity of the video signal. This will allow the best

use of the wide input common-mode range offered by the

WM8144-10. If the input video is positive going it is ad-

visable to clamp to Vcl (Lower clamp voltage). If the video

is negative going it is advisable to clamp to Vcu (Upper

clamp voltage). Regardless of where the video is clamped

the offset DAC is programmed to move the ADC output

corresponding to the reset level to an appropriate value

to maximise the ADC dynamic range. For Single Ended

operation it is recommended that the clamp voltage is set

to Vcm (Middle clamp voltage).

Figure 6: RLC Timing

RINP, GINP and BINP Input Impedence

The input impedence of the WM8144-10 analogue inputs

is dependent on the sampling frequency of the input sig-

nal and the configuration of the internal gain amplifiers.

The input impedence = 1/(Capacitance * frequency)

where the Capacitance value changes from 0.3pF for

minimum gain to 9.6pF for maximum gain. Table 1 illus-

trates the minimum and maximum input impedence at

different frequencies.

Sampling

Frequency

(MHz)

0.5

1

2

4

6

Impedence with

minimum gain

(MΩ)

6.6

3.3

1.6

0.8

0.5

Impedence with

maximum gain

(KΩ)

208

104

52

26

17

Table 1: Effects of Frequency on Input Impedence

Wolfson Microelectronics

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