25P10AV Просмотр технического описания (PDF) - STMicroelectronics

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25P10AV

1 Mbit, low voltage, Serial Flash memory with 50MHz SPI bus interface

STMicroelectronics 

M25P10-A

13 Revision history

Revision history

Table 24. Document revision history

Date

Revision

Changes

25-Feb-2001 1.0 Document written

VFQFPN8 package (MLP8) added. Clarification of descriptions of

12-Sep-2002 1.1 entering Standby Power mode from Deep Power-down mode, and of

terminating an instruction sequence or data-out sequence

Typical Page Program time improved. Write Protect setup and hold times

13-Dec-2002

1.2

specified, for applications that switch Write Protect to exit the Hardware

Protection mode immediately before a WRSR, and to enter the Hardware

Protection mode again immediately after

21-Feb-2003 1.3 Erroneous address ranges corrected in Memory Organisation table

24-Nov-2003

Table of contents, warning about exposed paddle on MLP8, and Pb-free

options added.

2.0 40MHz AC Characteristics table included as well as 25MHz. ICC3(max),

tSE(typ) and tBE(typ) values improved. Change of naming for VDFPN8

package

08-Mar-2005

Devices with Process technology Code X added (Read Identification

(RDID) and Table 20: AC Characteristics (50MHz Operation, Device

Grade 6)) added.

SO8 narrow package specifications updated.

3.0 Notes 1 and 2 removed from Table 23: Ordering information scheme.

Note 1 to Table 9: Absolute Maximum Ratings changed, note 2 removed

and TLEAD values removed.

Small text changes. End timing line of tSHQZ modified in Figure 25: Output

Timing.

01-Apr-2005

Read Identification (RDID), Deep Power-down (DP) and Release from

4.0

Deep Power-down and Read Electronic Signature (RES) instructions,

and Active Power, Standby Power and Deep Power-Down Modes

paragraph clarified.

01-Aug-2005

5.0

Updated Page Program (PP) instructions in Page Programming, Page

Program (PP) and Table 16: Instruction Times (Device Grade 6).

47/49

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