MAX5480A Просмотр технического описания (PDF) - Maxim Integrated
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MAX5480A Datasheet PDF : 7 Pages
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Table 2. Unipolar Binary Code Table
DIGITAL INPUT
MSB
LSB
11111111
ANALOG OUTPUT
-VREF
255
256
10000001
-VREF
129
256
10000000
-VREF
128
256
=
− VREF
2
01111111
-VREF
127
256
00000001
-VREF
1
256
00000000
-VREF
0
256
=
0
( ) ( ) NOTE : 1 LSB
=
2
−8
VREF
=
1
256
VREF
8-Bit Parallel DAC in
QSOP-16 Package
Table 3. Bipolar (Offset Binary) Code Table
DIGITAL INPUT
MSB
LSB
11111111
10000001
ANALOG OUTPUT
+VREF
127
128
+VREF
1
128
10000000
0
01111111
-VREF
1
128
00000001
-VREF
127
128
00000000
-VREF
128
128
( ) ( ) NOTE : 1 LSB
=
2
−7
VREF
=
1
128
VREF
10kΩ
10kΩ
REF
10kΩ
20kΩ
S8
20kΩ
S7
20kΩ
S6
20kΩ
S1
20kΩ
CS
WR
D7 (MSB)
INTERFACE LOGIC
D6
D5
OUT2
OUT1
RFB
10kΩ
D0 (LSB)
Figure 3. MAX5480 Functional Diagram
tCS
tCH
VDD
CS
WR
DATA IN
(D7–D0)
0
tWR
VDD
0
tDS
tDH
VIH DATA IN
VDD
STABLE
VIL
0
NOTES:
1. FOR THE MAX5480, ALL INPUT SIGNAL RISE AND FALL TIMES ARE MEASURED
FROM 10% TO 90% OF VDD. VDD = +5V, tr = tf = 20ns.
2. TIMING MEASUREMENT REFERENCE LEVEL IS (VIH + VIL) / 2.
Figure 4. Write-Cycle Timing Diagram
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