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XRT83VSH314

14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT

Exar Corporation 

XRT83VSH314

REV. 1.0.1

14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT

4.5.2 QRSS/PRBS GENERATION....................................................................................................................................... 28

TABLE 9: RANDOM BIT SEQUENCE POLYNOMIALS ........................................................................................................................... 28

4.6 TRANSMIT PULSE SHAPER AND FILTER ................................................................................................... 28

4.6.1 T1 SHORT HAUL LINE BUILD OUT (LBO) ............................................................................................................... 28

TABLE 10: SHORT HAUL LINE BUILD OUT ....................................................................................................................................... 28

4.6.2 ARBITRARY PULSE GENERATOR FOR T1 AND E1............................................................................................... 29

FIGURE 18. ARBITRARY PULSE SEGMENT ASSIGNMENT .................................................................................................................. 29

4.6.3 SETTING REGISTERS TO SELECT AN ARIBTRARY PULSE ................................................................................. 29

TABLE 11: TYPICAL ROM VALUES.................................................................................................................................................. 30

4.7 DMO (DIGITAL MONITOR OUTPUT) ............................................................................................................. 30

4.8 LINE TERMINATION (TTIP/TRING) ............................................................................................................... 30

FIGURE 19. TYPICAL CONNECTION DIAGRAM USING INTERNAL TERMINATION ................................................................................... 30

5.0 T1/E1 APPLICATIONS ........................................................................................................................ 31

5.1 LOOPBACK DIAGNOSTICS .......................................................................................................................... 31

5.1.1 LOCAL ANALOG LOOPBACK .................................................................................................................................. 31

FIGURE 20. SIMPLIFIED BLOCK DIAGRAM OF LOCAL ANALOG LOOPBACK ......................................................................................... 31

5.1.2 REMOTE LOOPBACK ................................................................................................................................................ 31

FIGURE 21. SIMPLIFIED BLOCK DIAGRAM OF REMOTE LOOPBACK.................................................................................................... 31

5.1.3 DIGITAL LOOPBACK ................................................................................................................................................. 32

FIGURE 22. SIMPLIFIED BLOCK DIAGRAM OF DIGITAL LOOPBACK ..................................................................................................... 32

5.1.4 DUAL LOOPBACK ..................................................................................................................................................... 32

FIGURE 23. SIMPLIFIED BLOCK DIAGRAM OF DUAL LOOPBACK ........................................................................................................ 32

5.2 84-CHANNEL T1/E1 MULTIPLEXER/MAPPER APPLICATIONS ................................................................. 33

FIGURE 24. SIMPLIFIED BLOCK DIAGRAM OF AN 84-CHANNEL APPLICATION ..................................................................................... 33

TABLE 12: CHIP SELECT ASSIGNMENTS.......................................................................................................................................... 33

5.3 LINE CARD REDUNDANCY .......................................................................................................................... 34

5.3.1 1:1 AND 1+1 REDUNDANCY WITHOUT RELAYS .................................................................................................... 34

5.3.2 TRANSMIT INTERFACE WITH 1:1 AND 1+1 REDUNDANCY .................................................................................. 34

FIGURE 25. SIMPLIFIED BLOCK DIAGRAM OF THE TRANSMIT INTERFACE FOR 1:1 AND 1+1 REDUNDANCY ......................................... 34

5.3.3 RECEIVE INTERFACE WITH 1:1 AND 1+1 REDUNDANCY..................................................................................... 34

FIGURE 26. SIMPLIFIED BLOCK DIAGRAM OF THE RECEIVE INTERFACE FOR 1:1 AND 1+1 REDUNDANCY ........................................... 35

5.3.4 N+1 REDUNDANCY USING EXTERNAL RELAYS ................................................................................................... 35

5.3.5 TRANSMIT INTERFACE WITH N+1 REDUNDANCY ................................................................................................ 36

FIGURE 27. SIMPLIFIED BLOCK DIAGRAM OF THE TRANSMIT INTERFACE FOR N+1 REDUNDANCY...................................................... 36

5.3.6 RECEIVE INTERFACE WITH N+1 REDUNDANCY ................................................................................................... 37

FIGURE 28. SIMPLIFIED BLOCK DIAGRAM OF THE RECEIVE INTERFACE FOR N+1 REDUNDANCY........................................................ 37

5.4 POWER FAILURE PROTECTION .................................................................................................................. 38

5.5 OVERVOLTAGE AND OVERCURRENT PROTECTION ............................................................................... 38

5.6 NON-INTRUSIVE MONITORING .................................................................................................................... 38

FIGURE 29. SIMPLIFIED BLOCK DIAGRAM OF A NON-INTRUSIVE MONITORING APPLICATION .............................................................. 38

5.7 ANALOG BOARD CONTINUITY CHECK ...................................................................................................... 39

FIGURE 30. ATP TESTING BLOCK DIAGRAM..................................................................................................................................... 39

FIGURE 31. TIMING DIAGRAM FOR ATP TESTING ........................................................................................................................... 39

5.7.1 TRANSMITTER TTIP AND TRING TESTING............................................................................................................. 39

5.7.2 RECEIVER RTIP AND RRING .................................................................................................................................... 40

6.0 MICROPROCESSOR INTERFACE BLOCK ....................................................................................... 41

TABLE 13: SELECTING THE MICROPROCESSOR INTERFACE MODE ................................................................................................... 41

FIGURE 32. SIMPLIFIED BLOCK DIAGRAM OF THE MICROPROCESSOR INTERFACE BLOCK.................................................................. 41

6.1 THE MICROPROCESSOR INTERFACE BLOCK SIGNALS ......................................................................... 42

TABLE 14: XRT84SH314S MICROPROCESSOR INTERFACE SIGNALS COMMON TO BOTH INTEL AND MOTOROLA MODES.................... 42

TABLE 15: INTEL MODE: MICROPROCESSOR INTERFACE SIGNALS .................................................................................................... 42

TABLE 16: MOTOROLA MODE: MICROPROCESSOR INTERFACE SIGNALS ........................................................................................... 43

6.2 INTEL MODE PROGRAMMED I/O ACCESS (ASYNCHRONOUS) .............................................................. 44

FIGURE 33. INTEL µP INTERFACE SIGNALS DURING PROGRAMMED I/O READ AND WRITE OPERATIONS............................................ 45

TABLE 17: INTEL MICROPROCESSOR INTERFACE TIMING SPECIFICATIONS........................................................................................ 45

6.3 MPC86X MODE PROGRAMMED I/O ACCESS (SYNCHRONOUS) ............................................................. 46

FIGURE 34. MOTOROLA MPC86X µP INTERFACE SIGNALS DURING PROGRAMMED I/O READ AND WRITE OPERATIONS.................... 47

TABLE 18: MOTOROLA MPC86X MICROPROCESSOR INTERFACE TIMING SPECIFICATIONS................................................................ 47

FIGURE 35. MOTOROLA 68K µP INTERFACE SIGNALS DURING PROGRAMMED I/O READ AND WRITE OPERATIONS............................ 48

TABLE 19: MOTOROLA 68K MICROPROCESSOR INTERFACE TIMING SPECIFICATIONS........................................................................ 48

7.0 REGISTER DESCRIPTIONS ............................................................................................................... 49

TABLE 20: MICROPROCESSOR REGISTER ADDRESS (ADDR[7:0]) ................................................................................................... 49

TABLE 21: MICROPROCESSOR REGISTER CHANNEL DESCRIPTION ................................................................................................... 49

TABLE 22: MICROPROCESSOR REGISTER GLOBAL DESCRIPTION ..................................................................................................... 50

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