XRT83VSH314 Просмотр технического описания (PDF) - Exar Corporation

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XRT83VSH314

14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT

Exar Corporation 

XRT83VSH314

14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT

TABLE OF CONTENTS

REV. 1.0.1

GENERAL DESCRIPTION .................................................................................................1

APPLICATIONS ...........................................................................................................................................1

FIGURE 1. BLOCK DIAGRAM OF THE XRT83VSH314 ........................................................................................................................ 1

FEATURES ......................................................................................................................................................2

PRODUCT ORDERING INFORMATION ..................................................................................................2

PIN OUT OF THE XRT83VSH314 ......................................................................................3

TABLE OF CONTENTS ............................................................................................................I

1.0 PIN DESCRIPTIONS ..............................................................................................................................4

MICROPROCESSOR.........................................................................................................................................4

RECEIVER SECTION........................................................................................................................................6

TRANSMITTER SECTION ..................................................................................................................................9

CONTROL FUNCTION ....................................................................................................................................11

CLOCK SECTION ..........................................................................................................................................11

JTAG SECTION............................................................................................................................................12

POWER AND GROUND ..................................................................................................................................13

NO CONNECTS.............................................................................................................................................15

2.0 CLOCK SYNTHESIZER .......................................................................................................................16

TABLE 1: INPUT CLOCK SOURCE SELECT........................................................................................................................................ 16

FIGURE 2. SIMPLIFIED BLOCK DIAGRAM OF THE CLOCK SYNTHESIZER ............................................................................................ 16

3.0 RECEIVE PATH LINE INTERFACE .....................................................................................................17

FIGURE 3. SIMPLIFIED BLOCK DIAGRAM OF THE RECEIVE PATH ...................................................................................................... 17

3.1 LINE TERMINATION (RTIP/RRING) .............................................................................................................. 17

3.1.1 INTERNAL TERMINATION ......................................................................................................................................... 17

TABLE 2: SELECTING THE INTERNAL IMPEDANCE ............................................................................................................................. 17

FIGURE 4. TYPICAL CONNECTION DIAGRAM USING INTERNAL TERMINATION .................................................................................... 17

TABLE 3: RECEIVE TERMINATIONS .................................................................................................................................................. 18

3.2 CLOCK AND DATA RECOVERY .................................................................................................................. 18

FIGURE 5. RECEIVE DATA UPDATED ON THE RISING EDGE OF RCLK .............................................................................................. 19

FIGURE 6. RECEIVE DATA UPDATED ON THE FALLING EDGE OF RCLK ............................................................................................ 19

TABLE 4: TIMING SPECIFICATIONS FOR RCLK/RPOS/RNEG .......................................................................................................... 19

3.2.1 RECEIVE SENSITIVITY .............................................................................................................................................. 20

FIGURE 7. TEST CONFIGURATION FOR MEASURING RECEIVE SENSITIVITY........................................................................................ 20

3.2.2 INTERFERENCE MARGIN ......................................................................................................................................... 20

FIGURE 8. TEST CONFIGURATION FOR MEASURING INTERFERENCE MARGIN .................................................................................... 20

3.2.3 GENERAL ALARM DETECTION AND INTERRUPT GENERATION ........................................................................ 21

FIGURE 9. INTERRUPT GENERATION PROCESS BLOCK..................................................................................................................... 21

3.2.4 FLSD (FIFO LIMIT STATUS DETECTION) ................................................................................................................ 22

3.3 JITTER ATTENUATOR ................................................................................................................................... 23

3.4 HDB3/B8ZS DECODER .................................................................................................................................. 23

FIGURE 10. SINGLE RAIL MODE WITH A FIXED REPEATING "0011" PATTERN ................................................................................... 23

FIGURE 11. DUAL RAIL MODE WITH A FIXED REPEATING "0011" PATTERN...................................................................................... 23

3.5 RXMUTE (RECEIVER LOS WITH DATA MUTING) ....................................................................................... 24

FIGURE 12. SIMPLIFIED BLOCK DIAGRAM OF THE RXMUTE FUNCTION ............................................................................................ 24

4.0 TRANSMIT PATH LINE INTERFACE ..................................................................................................25

FIGURE 13. SIMPLIFIED BLOCK DIAGRAM OF THE TRANSMIT PATH ................................................................................................... 25

4.1 TCLK/TPOS/TNEG DIGITAL INPUTS ............................................................................................................ 25

FIGURE 14. TRANSMIT DATA SAMPLED ON FALLING EDGE OF TCLK ............................................................................................... 25

FIGURE 15. TRANSMIT DATA SAMPLED ON RISING EDGE OF TCLK ................................................................................................. 25

TABLE 5: TIMING SPECIFICATIONS FOR TCLK/TPOS/TNEG ........................................................................................................... 26

4.2 HDB3/B8ZS ENCODER .................................................................................................................................. 26

TABLE 6: EXAMPLES OF HDB3 ENCODING...................................................................................................................................... 26

TABLE 7: EXAMPLES OF B8ZS ENCODING ...................................................................................................................................... 26

4.3 JITTER ATTENUATOR ................................................................................................................................... 27

TABLE 8: MAXIMUM GAP WIDTH FOR MULTIPLEXER/MAPPER APPLICATIONS .................................................................................... 27

4.4 TAOS (TRANSMIT ALL ONES) ...................................................................................................................... 27

FIGURE 16. TAOS (TRANSMIT ALL ONES) ...................................................................................................................................... 27

4.5 TRANSMIT DIAGNOSTIC FEATURES .......................................................................................................... 27

4.5.1 ATAOS (AUTOMATIC TRANSMIT ALL ONES)......................................................................................................... 28

FIGURE 17. SIMPLIFIED BLOCK DIAGRAM OF THE ATAOS FUNCTION............................................................................................... 28

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