L5150GJ Просмотр технического описания (PDF) - STMicroelectronics

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L5150GJ

5 V low dropout voltage regulator

STMicroelectronics 

Block diagram and pins description

L5150GJ

Table 2. Pins description

Pin

Name

Function

Reset adjustable threshold. Connected to an appropriate external

1

Res_Adj voltage divider, it allows to properly set the reset threshold down

to 3.5 V. Connect to GND if not needed.

Reset output. Internally connected to Vo through a 20 KΩ pull-up

2

Res

resistor. This pin is pulled low when Vo < Vo_th. Keep open if not

needed.

3

Vcr

Reset delay. Connect an external capacitor between Vcr pin and

ground to adjust the reset delay time. Keep open if not needed.

4

GND Ground reference.

5

NC

Not connected.

6

Vo

5 V regulated output. Block to GND with a ceramic capacitor

(Co ≥ 220 nF for regulator stability).

7

VS

Supply voltage, block directly to GND on the IC with a capacitor.

8

NC

Not connected.

9

En

Enable input. A high signal switches the regulator on. Connect to

VS if not needed.

10

EWi

Early warning input. This pin monitors the VS voltage level through

a resistor divider. Connect to VS if not needed.

11

NC

Not connected.

Early warning output. Internally connected to Vo through 20 KΩ

12

EWo

pull up resistor. This pin is pulled low when EWi is below bandgap

reference voltage. Keep open if not needed.

-

TAB

TAB is connected to the substrate of the chip: connect to GND or

leave open (see Figure 2).

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Doc ID 15540 Rev. 12

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