MAX8564 Просмотр технического описания (PDF) - Maxim Integrated

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MAX8564

±1%, Ultra-Low Output Voltage, Dual and Triple Linear n-FET Controllers

Maxim Integrated 

±1%, Ultra-Low Output Voltage, Dual and Triple

Linear n-FET Controllers

( ) RA

=

RB

×

⎡⎛

⎣⎢⎢⎝⎜

VOUT

VFB

⎞

⎠⎟

−

⎤

1⎥

⎦⎥

= RB ×

2 × VOUT − 1

To set the output voltage to 0.5V, disconnect RB from

FB_ and connect it to OUT_; this change maintains the

minimum load requirement on the output. In this case,

RA can vary from 1kΩ to 10kΩ.

Input and Output Capacitor Selection

The input filter capacitor aids in providing low input

impedance to the regulator and also reduces peak cur-

rents drawn from the power source during transient

conditions. Use a minimum 2.2µF ceramic capacitor

from IN_ (drain of the external pass n-MOSFET) to GND

(see Figures 1 and 2). If large line transients or load

transients are expected, increase the input capaci-

tance to help minimize output voltage changes.

The output filter capacitor and its equivalent series

resistance (ESR) contribute to the stability of the regula-

tor (see the Stability Compensation section) and affect

the load-transient response. If large step loads (no load

to full load) are expected, and a very fast response

(less than a few microseconds) is required, use a

100µF, 18mΩ POSCAP for the output capacitor. If a

larger capacitance is desired, keep the capacitance

ESR product (COUT x RESR) in the 1µs to 5µs range.

If the application expects smaller load steps (less than

50% of full load), then use a 6.8µF ceramic capacitor or

larger per ampere of maximum output current. This

option reduces the size and cost of the regulator circuit.

Note that some ceramic dielectrics exhibit large capaci-

tance variation with temperature. Use X7R or X5R

dielectrics to ensure sufficient capacitance at all operat-

ing temperatures. Tantalum and aluminum capacitors

are not recommended.

Power MOSFET Selection

The MAX8563/MAX8564/MAX8564A use an n-channel

MOSFET as the series pass transistor instead of a p-

channel MOSFET to reduce cost. The selected MOS-

FET must have a gate threshold voltage that meets the

following criteria:

VGS_MAX ≤ VDD - VOUT_

where VDD is the controller bias voltage, and VGS_MAX

is the maximum gate voltage required to yield the on-

resistance (RDS_ON) specified by the manufacturer’s

data sheet. RDS_ON multiplied by the maximum output

MAX8563

MAX8564

MAX8564A

FB_

OUT_

RA

RB

Figure 5. Adjustable Output Voltage

current (load current) is the maximum voltage dropout

across the MOSFET, VDS_MIN. Make sure that VDS_MIN

meets the condition below to avoid entering dropout,

where output voltage starts to decrease and any ripple

on the input also passes through to the output:

VIN_MIN > VDS_MIN + VOUT

where VIN_MIN is the minimum input voltage at the drain

of the MOSFET. VDS_MIN has a positive temperature

coefficient; therefore, the value of VDS_MIN at the highest

operating junction temperature should be used.

For thermal management, the maximum power dissipa-

tion in the MOSFET is calculated by:

PD = (VIN_MAX - VOUT) x IOUT_MAX

The MOSFET is typically in an SMT package. Refer to

the MOSFET data sheet for the PC board area needed

to meet the maximum operating junction temperature

required.

Stability Compensation

Connect a resistor, RC, and a capacitor, CC, in series

from the DRV_ pin to GND. The values of the compen-

sation network depend upon the external MOSFET

characteristics, the output current range, and the pro-

grammed output voltage. The following parameters are

needed from the MOSFET data sheet: the input capaci-

tance (CISS at VDS = 1V), the typical forward transcon-

ductance (gFS), and the current at which gFS was

measured (IDFS). Calculate the transconductance of

the FET at the maximum load current (IOUT_MAX):

gC(MAX) = gFS ×

IOUT _MAX

IDFS

______________________________________________________________________________________ 11

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