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MAX14821

IO-Link Device Transceiver

Maxim Integrated 

MAX14821

IO-Link Device Transceiver

The SPI register contents are unchanged while V5 is pres-

ent, regardless of the state of VCC and LDO33. The SPI

interface is not accessible and IRQ is not available when

UV is asserted due to a V5 or VL undervoltage event.

When the internal 3.3V LDO regulator voltage (VLDO33)

falls below the LDO33 undervoltage-lockout threshold,

the UV33Int bit in the Status register is set and IRQ

asserts. UV asserts if the UV33En bit in the Mode register

is set to 1.

The UV output deasserts once the undervoltage condi-

tion is removed; however, bits in the Status register and

the IRQ output are not cleared until the Status register

has been read.

Wake-Up Detection

The device detects an IO-Link wake-up condition on the

C/Q line in push-pull, high-side (PNP), or low-side (NPN)

operation modes. A wake-up condition is detected when

the C/Q output is shorted for 80Fs (typ). WU pulses low

for 190Fs (typ) when the device detects a wake-up pulse

on C/Q (Figure 5).

Set the WuIntEn bit in the Mode register to set the WuInt

bit in the Status register and generate an interrupt on

IRQ when a wake-up pulse is detected. WuInt is set

and IRQ asserts immediately after C/Q is released when

WuIntEn = 1.

Thermal Protection and Considerations

The internal LDOs and drivers can generate more power

than the package for the device can safely dissipate.

Ensure that the driver LDO loading is less than the pack-

age can dissipate. Total power dissipation for the device

is calculated using the following equation:

PTOTAL = PC/Q + PDO + P5 + PLDO33 + PQ +

PCLCQ + PCLDI

where PC/Q is the power generated in the C/Q driver,

PDO is the power dissipated by the DO driver, P5 and

PLDO33 are the power generated by the LDOs, PQ is the

quiescent power generated by the device, and PCLCQ

and PCLDI are the power generated in the C/Q and DI

current sinks.

Ensure that the total power dissipation is less than the

limits listed in the Absolute Maximum Ratings section.

Use the following to calculate the power dissipation (in

mW) due to the C/Q driver:

PC/Q = [IC/Q(max)] × [0.5 + 7 × IC/Q(max)]

Calculate the internal power dissipation of the DO driver

using the following equation:

PDO = [IDO(max)] × [0.5 + 7 × IDO(max)]

Calculate the power dissipation in the 5V LDO, V5, using

the following equation:

P5 = (VLDOIN - V5) × I5

where I5 includes the ILDO33 current sourced from

LDO33.

Calculate the power dissipated in the 3.3V LDO, LDO33,

using the following equation:

PLDO33 = 1.7V × ILDO33

Calculate the quiescent power dissipation in the device

using the following equation:

PQ = ICC(max) × VCC(max)

If the current sinks are enabled, calculate their associ-

ated power dissipation as:

PCLCQ = ILLM_C/Q(max) × VC/Q(max)

PCLDI = ILLM_DI(max) × VDI(max)

Overtemperature Warning

Bits in the Status and Mode registers are set when the

temperature of the device exceeds +115NC (typ). The

OTempInt bit in the Status register is set and IRQ asserts

when the OTemp bit in the Mode register is set. Read the

Status register to clear the OTempInt bit and IRQ.

The OTemp bit is cleared when the die temperature falls

to +95NC.

The device continues to operate normally unless the

die temperature reaches the +150NC thermal shutdown

threshold, when the device enters thermal shutdown.

Thermal Shutdown

When the die temperature rises above the +150°C (typ)

thermal shutdown threshold, the C/Q and DO drivers and

the C/Q and DI current loads are automatically turned off.

The internal 3.3V and 5V LDOs remain on during thermal

shutdown, if enabled. If the internal or external V5 supply

remains on during thermal shutdown (which is always

true in case of the internal V5 regulator), the register contents

are maintained and SPI communication is available.

When the die temperature falls below the thermal shutdown

threshold plus hysteresis, the C/Q and DO drivers and

C/Q and DI current sinks turn on automatically.

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