NE5565 Просмотр технического описания (PDF) - Philips Electronics
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NE5565 Datasheet PDF : 6 Pages
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Philips Semiconductors
Electronic ballast controller circuit
Product specification
NE5565
external LC network driven by the bridge. At frequencies above
resonance the primary voltage of the half-bridge LC load network
leads the primary current in phase. The protection logic senses the
LC network current phase relative to the half-bridge gate drive
voltage to determine if a resonant condition exists. The Iprim input
voltage represents the primary current signal from the external LC
network. If the voltage at Iprim is more positive than -100mV when
the gate drive signal is high, then a fault condition exists and the
half-bridge oscillator frequency is swept high.
Half-Bridge Oscillator
Is a triangle wave generator used to produce a square wave signal
for driving the half-bridge buffer circuit. The triangle wave appears
on the Ct capacitor output pin. The oscillator frequency is governed
by the value of the resistor connected to the Rt input and the value
of the Ct capacitor.
Output Buffer Drive
Convert the low level logic signals from the half-bridge oscillator and
pulse width modulator into a 10V drive signal for the power switches.
The OUTH half-bridge buffer/drive circuit will drive an external level
shift scheme which will then be used to operate the half-bridge
power switches. The OUTP output may directly drive a power
MOSFET switch or an external level shift/power MOSFET
combination.
Pulse Width Modulator
Generates a ramp voltage used to control the duty cycle of the PFC
SMPS. The frequency of the pulse width modulator is set by the
half-bridge oscillator. The ramp voltage appears at the CP output. It
is synchronized to the half-bridge oscillator so that the beginning of
the ramp occurs at the valley of the Ct triangle waveform. When the
ramp voltage at CP exceeds the voltage at the DC out pin in the DC
amplifier, the capacitor connected to CP is discharged. The period
of the PFC gate drive pulse correspond to the CP ramp time. The
maximum duty cycle, soft start function, and half-bridge off time are
all controlled by the external capacitor and resistors connected to
the DMAX pin.
Over Current Protection
An over current is sensed by an external resistor connected to the
current sense input pin, CSl. A voltage of minus 500mV at CSl
triggers the over current protection circuit this turns off the OUTP
output and forces the external capacitor connected to DMAX to
discharge when an over current condition occurs in the PFC input
circuit. An over current condition is usually produced during the turn
on transient of the SMPS or when the AC line voltage has a power
interruption.
Power Factor Amplifier
Senses the phase and amplitude of a peak rectified AC line voltage
in order to modulate the duty cycle of the PFC power switch. This is
done to improve the sinusoidal wave shape of the AC line current.
The power factor input is provided by the PF input pin. The voltage
at this pin is 1V when the AC line voltage reaches its peak and 0V
when the AC voltage is at its 0V crossing.
DC Error Amplifier
Provides negative feedback control of the PFC DC output voltage.
The DC pin senses the DC output voltage of the PFC through an
external resistor voltage divider and filter network. The reference
voltage for the DC error amplifier is VREF. The output of the
amplifier is available at the DC out pin and an external capacitor is
connected to this pin in order to remove switching frequency noise
before its signal is applied to the pulse width modulator in the PWM
oscillator circuit.
Lamp Current Rectifier
Is used to provide negative feedback control of the average lamp
current. An external lamp current transformer and load resistor are
used to convert the lamp current signal into a voltage. This voltage
is applied to the lamp current input pins, Li1 and Li2. The full wave
rectified output is provided at CRECT pin. External resistors and a
capacitor determine the gain and time constant of the circuit. A
differential error amplifier compares the voltage of CRECT to an
internal reference of 2/7 VREF and adjusts the half-bridge oscillator
frequency so that the error voltage is minimized. This forces the
average lamp current to be a constant.
Dimming
Dimming input should be an extra current put into charging C3 in
addition to the current from Pin 7. This creates the same condition
as higher voltage differential across Pins 8 and 9, hence, the IC
reacts as if there is too much power applied to the lamps.
1996 May 21
3
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