SFH6318T Просмотр технического описания (PDF) - Vishay Semiconductors
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SFH6318T Datasheet PDF : 8 Pages
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www.vishay.com
SFH6318, SFH6319
Vishay Semiconductors
CURRENT TRANSFER RATIO
PARAMETER
TEST CONDITION
PART SYMBOL MIN. TYP. MAX. UNIT
Current transfer ratio (1)
IF = 1.6 mA, VO = 0.4 V, VCC = 4.5 V
IF = 0.5 mA, VO = 0.4 V, VCC = 4.5 V
IF = 1.6 mA, VO = 0.4 V, VCC = 4.5 V
SFH6318
SFH6319
SFH6319
CTR
CTR
CTR
300
1600 2600
%
400
2000 3500
%
500
1600 2600
%
Notes
• Tamb = 0 °C to 70 °C. Typical values are specified at Tamb = 25 °C.
DC current transfer ratio is defined as the ratio of output collector current, IO, to the forward LED input current, IF times 100 %. Pin 7 open.
(1) Pin 7 open
SWITCHING CHARACTERISTICS (Tamb = 25 °C, unless otherwise specified)
PARAMETER
TEST CONDITION
PART SYMBOL
MIN.
Propagation delay time to logic
low at output
IF = 1.6 mA, RL = 2.2 kΩ SFH6318
tPHL
-
Propagation delay time to logic
low at output (1)
IF = 0.5 mA, RL = 4.7 kΩ SFH6319
tPHL
-
Propagation delay time to logic
low at output (1)
IF = 12 mA, RL = 270 Ω SFH6319
tPHL
-
Propagation delay time to logic
high at output
IF = 1.6 mA, RL = 2.2 kΩ SFH6318
tPLH
-
Propagation delay time to logic
high at output (1)
IF = 0.5 mA, RL = 4.7 kΩ SFH6319
tPLH
-
Propagation delay time to logic
high at output (1)
IF = 12 mA, RL = 270 Ω SFH6319
tPLH
-
Note
(1) Pin 7 open. Using a resistor between pin 5 and 7 will decrease gain and delay time.
TYP.
2
6
0.6
2
4
1.5
MAX.
10
25
1
35
60
7
UNIT
μs
μs
μs
μs
μs
μs
10 % duty cycle
1/f < 100 µs
1
Pulse
generator
IF
ZO = 5 0 Ω
2
tr = 5 n s
3
IF = monitor
4
Rm
I
0
8
+5V
V
7
RL
(saturated
response)
6
VO
0.1 µF
t PHL
5
C L= 15 pF
VO
(non-saturated
response)
Fig. 1 - Switching Test Circuit
1.5 V
90 %
10 %
tf
5V
t PLH
1.5 V
VOL
5V
90 %
10 %
tr
COMMON MODE TRANSIENT IMMUNITY
PARAMETER
TEST CONDITION
SYMBOL
MIN.
TYP.
MAX.
UNIT
Common mode transient immunity
at logic high level output (1)(2)
IF = 0 mA, RL = 2.2 kΩ,
VCM = 10 VP-P
|CMH|
-
1000
-
V/μs
Common mode transient immunity
at logic low level output (1)(2)
IF = 1.6 mA, RL = 2.2 kΩ,
VCM = 10 VP-P
|CML|
-
1000
-
V/μs
Notes
(1) Common mode transient immunity in logic high level is the maximum tolerable (positive) dVcm/dt on the leading edge of the common mode
pulse, VCM, to assure that the output will remain in a logic high state (i.e. VO > 2 V) common mode transient immunity in logic low level is the
maximum tolerable (negative) dVcm/dt on the trailing edge of the common mode pulse signal, VCM, to assure that the output will remain in a
logic low state (i.e.VO < 0.8 V).
(2) In applications where dv/dt may exceed 50 000 V/μs (such as state discharge) a series resistor, RCC should be included to protect IC from
destructively high surge currents. The recommended value is refer to figure 2.
RCC ≅ [(IV)/0.15 IF (mA)] kΩ.
Rev. 2.0, 14-Jul-15
3
Document Number: 83678
For technical questions, contact: optocoupleranswers@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
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