MSC8122(2006) Просмотр технического описания (PDF) - Freescale Semiconductor
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MSC8122 Datasheet PDF : 88 Pages
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Freescale Semiconductor
Technical Data
MSC8122
Rev. 13, 10/2006
MSC8122
Quad Core 16-Bit Digital Signal Processor
SC140
Extended Core
SC140
Extended Core
SC140
Extended Core
SC140
Extended Core
MQBus
Boot
ROM
M2
RAM
SQBus
128
128
64
IP Master
Memory
Controller
PLL/Clock PLL
JTAG Port JTAG
IPBus
32
System
Interface
64 Internal Local Bus
DMA
Bridge
Internal System Bus
SIU
Registers
64
Local Bus
32 Timers
UART
RS-232
4 TDMs
GPIO
GIC
8 Hardware
Semaphores
Ethernet
GPIO Pins
Interrupts
MII/RMII/SMII
Direct
Slave
Interface
(DSI)
Memory
Controller
DSI Port
32/64
System Bus
32/64
The raw processing power of
this highly integrated system-
on- a-chip device will enable
developers to create next-
generation networking
products that offer
tremendous channel
densities, while maintaining
system flexibility, scalability,
and upgradeability. The
MSC8122 is offered in three
core speed levels: 300, 400,
and 500 MHz.
What’s New?
Rev. 13 includes the following:
• Chapter 2 updates Table 2-13 to
add timings 17 and 18 for IRQs.
Figure 1. MSC8122 Block Diagram
The MSC8122 is a highly integrated system-on-a-chip that combines four SC140 extended cores with an RS-232
serial interface, four time-division multiplexed (TDM) serial interfaces, thirty-two general-purpose timers, a
flexible system interface unit (SIU), an Ethernet interface, and a multi-channel DMA engine. The four extended
cores can deliver a total 4800/6400/8000 DSP MMACS performance at 300/400/500 MHz.
Each core has four arithmetic logic units (ALUs), internal memory, a write buffer, and two interrupt controllers.
The MSC8122 targets high-bandwidth highly computational DSP applications and is optimized for wireless
transcoding and packet telephony as well as high-bandwidth base station applications. The MSC8122 delivers
enhanced performance while maintaining low power dissipation and greatly reducing system cost.
© Freescale Semiconductor, Inc., 2004, 2006. All rights reserved.
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