MSC8122(2006) Просмотр технического описания (PDF) - Freescale Semiconductor
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MSC8122 Datasheet PDF : 88 Pages
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1.1 Power Signals
Power Signals
Table 1-2. Power and Ground Signal Inputs
Signal Name
Description
VDD
VDDH
VCCSYN
GND
GNDSYN
Internal Logic Power
VDD dedicated for use with the device core. The voltage should be well-regulated and the input should be provided with
an extremely low impedance path to the VDD power rail.
Input/Output Power
This source supplies power for the I/O buffers. The user must provide adequate external decoupling capacitors.
System PLL Power
VCC dedicated for use with the system Phase Lock Loop (PLL). The voltage should be well-regulated and the input
should be provided with an extremely low impedance path to the VCC power rail.
System Ground
An isolated ground for the internal processing logic and I/O buffers. This connection must be tied externally to all chip
ground connections, except GNDSYN. The user must provide adequate external decoupling capacitors.
System PLL Ground
Ground dedicated for system PLL use. The connection should be provided with an extremely low-impedance path to
ground.
1.2 Clock Signals
Signal Name
CLKIN
CLKOUT
Reserved
Type
Input
Output
Input
Table 1-3. Clock Signals
Signal Description
Clock In
Primary clock input to the MSC8122 PLL.
Clock Out
The bus clock.
Reserved. Pull down to ground.
1.3 Reset and Configuration Signals
Table 1-4. Reset and Configuration Signals
Signal Name
PORESET
RSTCONF
Type
Input
Input
Signal Description
Power-On Reset
When asserted, this line causes the MSC8122 to enter power-on reset state.
Reset Configuration
Used during reset configuration sequence of the chip. A detailed explanation of its function is provided in
the MSC8122 Reference Manual. This signal is sampled upon deassertion of PORESET.
HRESET
SRESET
Note:
When PORESET is deasserted, the MSC8122 also samples the following signals:
• BM[0–2]—Selects the boot mode.
• MODCK[1–2]—Selects the clock configuration.
• SWTE—Enables the software watchdog timer.
• DSISYNC, DSI64, CNFGS, and CHIP_ID[0–3]—Configures the DSI.
Refer to Table 1-5 for details on these signals.
Input/Output Hard Reset
When asserted as an input, this signal causes the MSC8122 to enter hard reset state. After the device
enters a hard reset state, it drives the signal as an open-drain output.
Input/Output Soft Reset
When asserted as an input, this signal causes the MSC8122 to enter soft reset state. After the device
enters a soft reset state, it drives the signal as an open-drain output.
MSC8122 Technical Data, Rev. 13
Freescale Semiconductor
1-3
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