SMS44S Просмотр технического описания (PDF) - Summit Microelectronics

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производитель

SMS44S

Highly Programmble Voltage Supervisory Circuit

Summit Microelectronics 

SMS44

Sequencing

Enabled

V0

No

>VPTH?

Yes

tPDLY1

Turn On PUP#1

V1

No

>VPTH?

Yes

tPDLY2

Turn On PUP#2

V2

No

>VPTH?

Yes

tPDLY3

Turn On PUP#3

2047 Fig07 2.1

Figure 7. Sequence Flow Chart

The delay from VPTH0 until PUP#1 low is tPDLY1. There is

a similar tPDLYX delay for V1 to PUP#2 and V2 to PUP#3.

They are programmed in register 7. See Figure 5.

Sequencing will always occur as indicated in the flow

chart.

MEMORY OPERATION

Data for the configuration registers and the memory array

are read and written via an industry standard two-wire

interface. The bus was designed for two-way, two-line

serial communication between different integrated cir-

cuits. The two lines are a serial data line (SDA) and a serial

clock line (SCL). The SDA line must be connected to a

positive supply by a pull-up resistor, located somewhere

on the bus. See Memory Operating Characteristics:

Table 8 and Figure 8.

2047 2.3 10/23/00

SUMMIT MICROELECTRONICS, Inc.

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