SPT7852 Просмотр технического описания (PDF) - Cadeka Microcircuits LLC.
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SPT7852 Datasheet PDF : 11 Pages
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ABSOLUTE MAXIMUM RATINGS (Beyond which damage may occur)1 25 °C
Supply Voltages
AVDD ......................................................................... +6 V
DVDD ......................................................................... +6 V
Input Voltages
Analog Input ................................. –0.5 V to AVDD +0.5 V
VRef .............................................. –1.5 V to AVDD +0.8 V
CLK Input ................................................................... VDD
AVDD – DVDD ...................................................... ±100 mV
Output
Digital Outputs ....................................................... 10 mA
Temperature
Operating Temperature ................................... 0 to 70 °C
Junction Temperature ........................................... 175 °C
Lead Temperature, (soldering 10 seconds) .......... 300 °C
Storage Temperature ............................... –65 to +150 °C
Note: 1. Operation at any Absolute Maximum Rating is not implied. See Electrical Specifications for proper nominal
applied conditions in typical applications.
ELECTRICAL SPECIFICATIONS FOR EACH CHANNEL
TA = TMIN to TMAX, AVDD = DVDD = +5.0 V, VIN =0 to 4 V, ƒS =20 MSPS, ƒCLK =40 MHz, VRHS =4.0 V, VRLS =0.0 V, unless otherwise specified.
PARAMETERS
TEST
CONDITIONS
TEST
LEVEL
MIN
TYP
MAX UNITS
Resolution
10
Bits
DC Accuracy
Integral Nonlinearity
Differential Nonlinearity
Analog Input
Input Voltage Range
Input Resistance
Input Capacitance
Input Bandwidth
Offset
Gain Error
Full Power
IV
±1.0
LSB
IV
±1.0
LSB
V
VRLS
VRHS V
V
50
kΩ
V
5.0
pF
V
35
MHz
VI
±2.0
LSB
VI
±2.0
LSB
Reference Input
Resistance
Voltage Range
VRLS
VRHS
VRHS – VRLS
∆(VRHF – VRHS)
∆(VRLS – VRLF)
Conversion Characteristics
Maximum Conversion Rate1
Minimum Conversion Rate1
Pipeline Delay (Latency)
Aperture Delay Time
Aperture Jitter Time
VRHS – VRLS
VI
350
425
500 Ω
IV
0
-
2.0 V
IV
3.0
-
AVDD V
V
1.0
4.0
5.0 V
V
150
mV
V
150
mV
VI
20
MHz
IV
100 kHz
IV
12 Clock Cycles
V
5
ns
V
15
ps
Dynamic Performance
Effective Number of Bits
ƒIN=3.58 MHz
ƒIN= 10 MHz
VI
8.4
8.9
Bits
VI
7.9
8.4
Bits
12X Clock required.
SPT7852
2
1/12/00
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