SPT7852SCU Просмотр технического описания (PDF) - Signal Processing Technologies
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SPT7852SCU Datasheet PDF : 11 Pages
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Figure 3 – Timing Diagram 2
Analog In
(Channel A)
Analog In
(Channel B)
Clock In
Reset
Sampling Clock
(Internal)
Data Out
(Channel A)
Data Out
(Channel B)
Data Valid
1
2
3
4
5
6
7
8
11
10
9
Invalid
Invalid
Valid
12 34
Valid
12 34
Table II – Timing Parameters Table
DESCRIPTION PARAMETERS MIN TYP MAX UNITS
Conversion Time
Clock Period
Clock Duty Cycle
Output Delay
(15 pF Load)
DAV Pulse Width
Clock to DAV
Data Set Up Time
Data Hold Time
tc
tCLK
tOD
tDAV
td
tSet
tHold
2*tCLK
ns
25
ns
40 50 60 %
11
ns
tCLK
ns
15
ns
22
28
SPT
7
SPT7852
1/12/00
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